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? 1996-2013 microchip technology inc. preliminary ds40143e-page 1 pic16c55x devices included in this data sheet: referred to collectively as pic16c55x. ? pic16c554 ? pic16c557 ? pic16c558 high performance risc cpu: ? only 35 instructions to learn ? all single-cycle instructions (200 ns), except for program branches which are two-cycle ? operating speed: - dc - 20 mhz clock input - dc - 20 ns instruction cycle ? interrupt capability ? 16-18 special function hardware registers ? 8-level deep hardware stack ? direct, indirect and relative addressing modes peripheral features: ? 13-22 i/o pins with individual direction control - pull-up resistors on portb ? high current sink/source for direct led drive ? timer0: 8-bit timer/counter with 8-bit programma- ble prescaler pin diagram device program memory data memory pic16c554 512 80 pic16c557 2 k 128 pic16c558 2 k 128 ra1 ra0 osc2/clkout v dd rb7 rb6 rb5 rb4 osc1/clkin ra2 ra3 mclr /vpp v ss rb0/int rb1 rb2 rb3 ra4/t0cki pic16c554/558 pdip, soic, windowed cerdip ssop 2 3 4 5 6 7 8 9 ?1 18 17 15 14 13 12 11 10 16 ra1 ra0 osc2/clkout v dd rb7 rb6 rb5 osc1/clkin ra2 ra3 mclr/ v pp v ss rb1 rb2 ra4/t0cki pic16c557 rb4 rb3 2 3 4 5 6 7 8 9 10 ?1 19 18 16 15 14 13 12 11 17 20 21 22 23 24 25 26 27 28 n/c ra5 rb0/int rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 pdip, soic, windowed cerdip ra1 ra0 osc2/clkout v dd rb7 rb6 rb5 osc1/clkin ra2 ra3 mclr/ v pp v ss rb1 rb2 ra4/t0cki pic16c557 rb4 rb3 2 3 4 5 6 7 8 9 10 ?1 19 18 16 15 14 13 12 11 17 20 21 22 23 24 25 26 27 28 ra5 rb0/int rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 ssop v ss ra1 ra0 osc2/clkout v dd rb7 rb6 rb5 rb4 osc1/clkin ra2 ra3 mclr /vpp v ss rb0/int rb1 rb2 rb3 ra4/t0cki pic16c554/558 2 3 4 5 6 7 8 9 ?1 20 19 17 15 14 13 12 11 18 v ss 10 v dd 16 eprom-based 8-bit cmos microcontrollers
pic16c55x ds40143e-page 2 preliminary ? 1996-2013 microchip technology inc. special microcontroller features: ? power-on reset (por) ? power-up timer (pwrt) and oscillator start-up timer (ost) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? programmable code protection ? power saving sleep mode ? selectable oscillator options ? serial in-circuit programming (via two pins) ? four user programmable id locations cmos technology: ? low power, high speed cmos eprom technol- ogy ? fully static design ? wide operating voltage range - 2.5v to 5.5v ? commercial, industrial and extended temperature range ? low power consumption - < 2.0 ma @ 5.0v, 4.0 mhz -15 ? a typical 3.0v, 32 khz -< 1.0 ? a typical standby current @ 3.0v device differences note: for additional information on enhance- ments, see appendix a device voltage range oscillator pic16c554 2.5 - 5.5 (note 1) pic16c557 2.5 - 5.5 (note 1) pic16c558 2.5 - 5.5 (note 1) note 1: if you change from this device to another device, please verify oscillator characteristics in your application.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 3 pic16c55x table of contents 1.0 general description......................................................................................................... ............................................................. 5 2.0 pic16c55x device varieties .................................................................................................. ..................................................... 7 3.0 architectural overview ...................................................................................................... ........................................................... 9 4.0 memory organization ......................................................................................................... ........................................................ 13 5.0 i/o ports ................................................................................................................... .................................................................. 23 6.0 special features of the cpu................................................................................................. ..................................................... 31 7.0 timer0 module ............................................................................................................... ............................................................ 47 8.0 instruction set summary ..................................................................................................... ....................................................... 53 9.0 development support......................................................................................................... ........................................................ 67 10.0 electrical specifications.................................................................................................. ............................................................ 73 11.0 packaging information...................................................................................................... .......................................................... 87 appendix a: enhancements........................................................................................................ ..................................................... 97 appendix b: compatibility ...................................................................................................... ......................................................... 97 index .......................................................................................................................... .......................................................................... 99 on-line support................................................................................................................ ................................................................. 101 systems information and upgrade hot line ....................................................................................... ............................................... 101 reader response ................................................................................................................ .............................................................. 102 product identification system .................................................................................................. .......................................................... 103 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literatu re center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, pleas e specify which device, revisi on of silicon and data sheet (inclu de liter- ature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
pic16c55x ds40143e-page 4 preliminary ? 1996-2013 microchip technology inc. notes:
? 1996-2013 microchip technology inc. preliminary ds40143e-page 5 pic16c55x 1.0 general description the pic16c55x are 18, 20 and 28-pin eprom-based members of the versatile pic16cxx family of low cost, high performance, cmos, fully-static, 8-bit microcontrollers. all pic ? microcontrollers employ an advanced risc architecture. the pic16c55x have enhanced core fea- tures, eight-level deep stack, and multiple internal and external interrupt sources. the separate instruction and data buses of the harvard architecture allow a 14- bit wide instruction word with the separate 8-bit wide data. the two-stage instruction pipeline allows all instructions to execute in a single-cycle, except for pro- gram branches (which require two cycles). a total of 35 instructions (reduced instruction set) are available. additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. pic16c55x microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. the pic16c554 has 80 bytes of ram. the pic16c557 and pic16c558 have 128 bytes of ram. the pic16c554 and pic16c558 have 13 i/o pins and an 8- bit timer/counter with an 8-bit programmable prescaler. the pic16c557 has 22 i/o pins and an 8-bit timer/ counter with an 8-bit programmable prescaler. pic16c55x devices have special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. there are four oscillator options, of which the single pin rc oscillator provides a low cost solution, the lp oscillator minimizes power consumption, xt is a standard crystal, and the hs is for high speed crystals. the sleep (power-down) mode offers power saving. the user can wake-up the chip from sleep through several external and internal interrupts and reset. a highly reliable watchdog timer, with its own on-chip rc oscillator, provides protection against software lock-up. a uv-erasable cerdip packaged version is ideal for code development while the cost effective one-time programmable (otp) version is suitable for production in any volume. table 1-1 shows the features of the pic16c55x mid- range microcontroller families. a simplified block diagram of the pic16c55x is shown in figure 3-1. the pic16c55x series fit perfectly in applications ranging from motor control to low power remote sen- sors. the eprom technology makes customization of application programs (detection levels, pulse genera- tion, timers, etc.) extremely fast and convenient. the small footprint packages make this microcontroller series perfect for all applications with space limitations. low cost, low power, high performance, ease of use and i/o flexibility make the pic16c55x very versatile. 1.1 family and upward compatibility users familiar with the family of microcontrollers will realize that this is an enhanced version of the architec- ture. please refer to appendix a for a detailed list of enhancements. code written for can be easily ported to pic16c55x family of devices (appendix b). the pic16c55x family fills the niche for users wanting to migrate up from the family and not needing various peripheral features of other members of the pic16xx mid-range microcontroller family. 1.2 development support the pic16c55x family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low cost development programmer and a full-featured programmer.
pic16c55x ds40143e-page 6 preliminary ? 1996-2013 microchip technology inc. table 1-1: pic16c55x family of devices pic16c554 pic16c557 pic16c558 clock maximum frequency of operation (mhz) 20 20 20 memory eprom program memory (x14 words) 512 2k 2k data memory (bytes) 80 128 128 peripherals timer module(s) tmr0 tmr0 tmr0 features interrupt sources 3 3 3 i/o pins 13 22 13 voltage range (volts) 2.5-5.5 2.5-5.5 2.5-5.5 brown-out reset ? ? ? packages 18-pin dip, soic; 20-pin ssop 28-pin dip, soic; 28-pin ssop 18-pin dip, soic, ssop all pic ? family devices have power-on reset, selectable watchdog timer, selectable code protect and high ? i/o current capability. all pic16c55x family devices use serial programming with clock pin rb6 and data pin rb7.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 7 pic16c55x 2.0 pic16c55x device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in the pic16c55x product identification system section at the end of this data sheet. when placing orders, please use this page of the data sheet to specify the correct part number. 2.1 uv erasable devices the uv erasable version, offered in cerdip package, is optimal for prototype development and pilot programs. this version can be erased and reprogrammed to any of the oscillator modes. microchip's picstart ?? and promate ? programmers both support programming of the pic16c55x. 2.2 one-time programmable (otp) devices the availability of otp devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. in addition to the program memory, the configuration bits must also be programmed. 2.3 quick-turnaround production (qtp) devices microchip offers a qtp programming service for factory production orders. this service is made available for users who choose not to program a medium-to-high quantity of units and whose code pat- terns have stabilized. the devices are identical to the otp devices, but with all eprom locations and config- uration options already programmed by the factory. certain code and prototype verification procedures apply before production shipments are available. please contact your microchip technology sales office for more details. 2.4 serialized quick-turnaround production (sqtp sm ) devices microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number which can serve as an entry code, password or id number.
pic16c55x ds40143e-page 8 preliminary ? 1996-2013 microchip technology inc. notes:
? 1996-2013 microchip technology inc. preliminary ds40143e-page 9 pic16c55x 3.0 architectural overview the high performance of the pic16c55x family can be attributed to a number of architectural features commonly found in risc microprocessors. to begin with, the pic16c55x uses a harvard architecture in which program and data are accessed from separate memories using separate busses. this improves bandwidth over traditional von neumann architecture where program and data are fetched from the same memory. separating program and data memory further allows instructions to be sized differently from 8-bit wide data words. instruction opcodes are 14-bit wide making it possible to have all single word instructions. a 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execution of instructions. consequently, all instructions (35) execute in a single- cycle (200 ns @ 20 mhz) except for program branches. the table below lists the memory (eprom and ram). the pic16c554 addresses 512 x 14 on-chip program memory. the pic16c557 and pic16c558 addresses 2 k x 14 program memory. all program memory is inter- nal. the pic16c55x can directly or indirectly address its register files or data memory. all special function registers, including the program counter, are mapped into the data memory. the pic16c55x has an orthog- onal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ?special optimal situations? make programming with the pic16c55x simple yet efficient. in addition, the learning curve is reduced significantly. the pic16c55x devices contain an 8-bit alu and working register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between data in the working register and any register file. the alu is 8-bits wide and capable of addition, subtraction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's complement in nature. in two-operand instructions, typically one operand is the working register (w register). the other operand is a file register or an immediate constant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. a simplified block diagram is shown in figure 3-1, with a description of the device pins in table 3-1. device program memory (eprom) data memor (ram) pic16c554 512 80 pic16c557 2 k 128 pic16c558 2 k 128
pic16c55x ds40143e-page 10 preliminary ? 1996-2013 microchip technology inc. figure 3-1: block diagram eprom program memory 2k x 14 13 data bus 8 14 program bus instruction reg program counter 8-level stack (13-bit) ram file registers 128 x 8 direct addr 7 8 addr mux indirect addr 8 fsr status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout v pp v dd , v ss timer0 3 porta portb ra1 ra4/t0cki rb0/int rb7:rb1 8 8 ram addr (1) ra0 ra2 ra3 512 x 14 to 80 x 8 to device program memory data memory pic16c554 512 x 14 80 x 8 pic16c557 2 k x 14 128 x 8 pic16c558 2 k x 14 128 x 8 portc (2) rc7:rc0 note 1: higher order bits are from status register. 2: pic16c557 only.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 11 pic16c55x table 3-1: pic16c55x pinout description name pin number pin type buffer type pdip soic ssop description osc1/clkin 16 16 18 i st/cmos oscillator crystal input/external clock source output. osc2/clkout 15 15 17 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 4 4 4 i/p st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. ra0 17 17 19 i/o st bi-directional i/o port ra1 18 18 20 i/o st bi-directional i/o port ra2 1 1 1 i/o st bi-directional i/o port ra3 2 2 2 i/o st bi-directional i/o port ra4/t0cki 3 3 3 i/o st bi-directional i/o port or external clock input for tmr0. output is open drain type. rb0/int 6 6 7 i/o ttl/st (1) bi-directional i/o port can be software programmed for internal weak pull-up. rb0/int can also be selected as an external interrupt pin. rb1 7 7 8 i/o ttl bi-directional i/o port can be software programmed for internal weak pull-up. rb2 8 8 9 i/o ttl bi-directional i/o port can be software programmed for internal weak pull-up. rb3 9 9 10 i/o ttl bi-directional i/o port can be software programmed for internal weak pull-up. rb4 10 10 11 i/o ttl bi-directional i/o port can be software programmed for internal weak pull-up. interrupt-on-change pin. rb5 11 11 12 i/o ttl bi-directional i/o port can be software programmed for internal weak pull-up. interrupt-on-change pin. rb6 12 12 13 i/o ttl/st (2) bi-directional i/o port can be software programmed for internal weak pull-up. interrupt-on-change pin. serial pro- gramming clock. rb7 13 13 14 i/o ttl/st (2) bi-directional i/o port can be software programmed for internal weak pull-up. interrupt-on-change pin. serial pro- gramming data. rc0 (3) 18 18 18 i/o ttl bi-directional i/o port input buffer. rc1 (3) 19 19 19 i/o ttl bi-directional i/o port input buffer. rc2 (3) 20 20 20 i/o ttl bi-directional i/o port input buffer. rc3 (3) 21 21 21 i/o ttl bi-directional i/o port input buffer. rc4 (3) 22 22 22 i/o ttl bi-directional i/o port input buffer. rc5 (3) 23 23 23 i/o ttl bi-directional i/o port input buffer. rc6 (3) 24 24 24 i/o ttl bi-directional i/o port input buffer. rc7 (3) 25 25 25 i/o ttl bi-directional i/o port input buffer. v ss 5 5 5,6 p ? ground reference for logic and i/o pins. v dd 14 14 15,16 p ? positive supply for logic and i/o pins. legend: o = output i/o = input/output p = power ? ? = not used i = input st = schmitt trigger input ? ttl = ttl input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: pic16c557 only.
pic16c55x ds40143e-page 12 preliminary ? 1996-2013 microchip technology inc. 3.1 clocking scheme/instruction cycle the clock input (osc1/clkin pin) is internally divided by four to generate four non-overlapping quadrature clocks namely q1, q2, q3 and q4. internally, the program counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruction is decoded and executed during the following q1 through q4. the clocks and instruction execution flow are shown in figure 3-2. 3.2 instruction flow/pipelining an ?instruction cycle? consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ?instruction register (ir)? in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-2: clock /instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clocks all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ?flushed? from the pipeline while the new instruction is being fetched and then executed. 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 fetch 4 flush fetch sub_1 execute sub_1
? 1996-2013 microchip technology inc. preliminary ds40143e-page 13 pic16c55x 4.0 memory organization 4.1 program memory organization the pic16c55x has a 13-bit program counter capable of addressing an 8 k x 14 program memory space. only the first 512 x 14 (0000h - 01ffh) for the pic16c554 and 2k x 14 (0000h - 07ffh) for the pic16c557 and pic16c558 are physically imple- mented. accessing a location above these boundaries will cause a wrap-around within the first 512 x 14 spaces in the pic16c554, or 2k x 14 space of the pic16c558 and pic16c557. the reset vector is at 0000h and the interrupt vector is at 0004h (figure 4-1, figure 4-2). figure 4-1: program memory map and stack for the pic16c554 figure 4-2: program memory map and stack for the pic16c557 and pic16c558 4.2 data memory organization the data memory (figure 4-3 through figure 4-5) is partitioned into two banks which contain the general purpose registers (gpr) and the special function registers (sfr). bank 0 is selected when the rp0 bit (status <5>) is cleared. bank 1 is selected when the rp0 bit is set. the special function registers are located in the first 32 locations of each bank. register locations 20-6fh (bank 0) on the pic16c554 and 20- 7fh (bank 0) and a0-bfh (bank 1) on the pic16c558 and pic16c557 are general purpose registers imple- mented as static ram. some special purpose registers are mapped in bank 1. 4.2.1 general purpose register file the register file is organized as 80 x 8 in the pic16c554 and 128 x 8 in the pic16c557 and pic16c558. each can be accessed either directly or indirectly through the file select register, fsr (section 4.4). pc<12:0> 13 000h 0004 0005 01ffh 0200h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw stack level 2 pc<12:0> 13 000h 0004 0005 07ffh 0800h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw stack level 2
pic16c55x ds40143e-page 14 preliminary ? 1996-2013 microchip technology inc. figure 4-3: data memory map for the pic16c554 figure 4-4: data memory map for the pic16c557 indf (1) tmr0 pcl status fsr porta portb pclath intcon indf (1) option pcl status fsr trisa trisb pclath intcon pcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register 7fh ffh bank 0 bank 1 file address 6fh 70h unimplemented data memory locations, read as '0'. note 1: not a physical register. file address tmr0 pcl status fsr porta portb pclath intcon indf (1) option pcl status fsr trisa trisb pclath intcon pcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register 7fh ffh bank 0 bank 1 file address bfh c0h unimplemented data memory locations, read as '0'. note 1: not a physical register. file address general purpose register indf (1) portc trisc
? 1996-2013 microchip technology inc. preliminary ds40143e-page 15 pic16c55x figure 4-5: data memory map for the pic16c558 4.2.2 special function registers the special function registers are registers used by the cpu and peripheral functions for controlling the desired operation of the device (table 4-1). these registers are static ram. the special function registers can be classified into two sets (core and peripheral). the special function registers associated with the ?core? functions are described in this section. those related to the operation of the peripheral features are described in the section of that peripheral feature. indf (1) tmr0 pcl status fsr porta portb pclath intcon indf (1) option pcl status fsr trisa trisb pclath intcon pcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register 7fh ffh bank 0 bank 1 file address bfh c0h unimplemented data memory locations, read as '0'. note 1: not a physical register. file address general purpose register
pic16c55x ds40143e-page 16 preliminary ? 1996-2013 microchip technology inc. table 4-1: special registers for the pic16c55x address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por reset detail on page: bank 0 00h indf addressing this locati on uses contents of fsr to address data memory (not a physical register) xxxx xxxx 21 01h tmr0 timer0 module?s register xxxx xxxx 47 02h pcl program counter's (pc) least significant byte 0000 0000 21 03h status irp (2) rp1 (2) rp0 to pd zdcc 0001 1xxx 17 04h fsr indirect data memory address pointer xxxx xxxx 21 05h porta ? ? ? ra4 ra3 ra2 ra1 ra0 ---x xxxx 23 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx 25 07h portc (4) rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx 27 08h ? unimplemented ? ? 09h ? unimplemented ? ? 0ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 21 0bh intcon gie (3) t0ie inte rbie t0if intf rbif 0000 000x 19 0ch ? unimplemented ? ? 0dh-1eh ? unimplemented ? ? 1fh ? unimplemented ? ? bank 1 80h indf addressing this locati on uses contents of fsr to address data memory (not a physical register) xxxx xxxx 21 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 18 82h pcl program counter's (pc) least significant byte 0000 0000 21 83h status ? ?rp0to pd zdcc 0001 1xxx 17 84h fsr indirect data memory address pointer xxxx xxxx 21 85h trisa ? ? ? trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 23 86h trisb trisb7 trisb6 trisb5 tri sb4 trisb3 trisb2 trisb1 trisb0 1111 1111 25 87h trisc (4) trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 27 88h ? unimplemented ? ? 89h ? unimplemented ? ? 8ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 21 8bh intcon gie (3) t0ie inte rbie t0if intf rbif 0000 000x 19 8ch ? unimplemented ? ? 8dh ? unimplemented ? ? 8eh pcon ? ? ? ? ? ?por ? ---- --0- 20 8fh-9eh ? unimplemented ? ? 9fh ? unimplemented ? ? legend: ? = unimplemented locations read as ?0?, u = unchanged, x = unknown, q = value depends on condition, ? shaded = unimplemented note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation. 2: irp & rp1 bits are reserved, always maintain these bits clear. 3: bit 6 of intcon register is reserved for future use. always maintain this bit as clear. 4: pic16c557 only.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 17 pic16c55x 4.2.2.1 status register the status register, shown in figure 4-2, contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as the destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000uu1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf , swapf and movwf instructions be used to alter the status register because these instructions do not affect any status bits. for other instructions, not affect- ing any status bits, see the ?instruction set summary?. register 4-1: status register (address 03h or 83h) note 1: the irp and rp1 bits (status<7:6>) are not used by the pic16c55x and should be programmed as ?0'. use of these bits as general purpose r/w bits is not recommended, since this may affect upward compatibility with future products. 2: the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. reserved reserved r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdcc bit7 bit0 bit 7 irp : register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) the irp bit is reserved on the pic16c55x, always maintain this bit clear bit 6-5 rp1:rp0 : register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes. the rp1 bit is reserved on the pic16c55x, always maintain this bit clear. bit 4 to : timeout bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt timeout occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit ( addwf, addlw, sublw, subwf instructions) (for borrow the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0 c : carry/borrow bit ( addwf, addlw,sublw,subwf instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate (rrf, rlf) instructions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16c55x ds40143e-page 18 preliminary ? 1996-2013 microchip technology inc. 4.2.2.2 option register the option register is a readable and writable register which contains various control bits to configure the tmr0/wdt prescaler, the external rb0/int interrupt, tmr0 and the weak pull-ups on portb. register 4-2: option register (address 81h) note 1: to achieve a 1:1 prescaler assignment for tmr0, assign the prescaler to the wdt (psa = 1). r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit7 bit0 bit 7 rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5 t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0 : prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
? 1996-2013 microchip technology inc. preliminary ds40143e-page 19 pic16c55x 4.2.2.3 intcon register the intcon register is a readable and writable register which contains the various enable and flag bits for all interrupt sources. register 4-3: intcon register (address 0bh or 8bh) note: interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). r/w-0 reserved r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie ? t0ie inte rbie t0if intf rbif bit7 bit0 bit 7 gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6 reserved: for future use. always maintain this bit clear. bit 5 t0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 inte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3 rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 t0if : tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0 rbif : rb port change interrupt flag bit 1 = when at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic16c55x ds40143e-page 20 preliminary ? 1996-2013 microchip technology inc. 4.2.2.4 pcon register the pcon register contains a flag bit to differentiate between a power-on reset, an external mclr reset or wdt reset. see section 6.3 and section 6.4 for detailed reset operation. register 4-4: pcon register (address 8eh) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 ? ? ? ? ? ?por ? bit7 bit0 bit 7-2 unimplemented: read as '0' bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = power-on reset occurred bit 0 unimplemented: read as '0' legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1996-2013 microchip technology inc. preliminary ds40143e-page 21 pic16c55x 4.3 pcl and pclath the program counter (pc) is 13-bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high bits (pc<12:8>) are not directly readable or writable and come from pclath. on any reset, the pc is cleared. figure 4-6 shows the two situations for the loading of the pc. the upper example in the figure shows how the pc is loaded on a write to pcl (pclath<4:0> ? pch). the lower exam- ple in figure 4-6 shows how the pc is loaded during a call or goto instruction (pclath<4:3> ? pch). figure 4-6: loading of pc in ? different situations 4.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256 byte block). refer to the application note ?implementing a table read" (an556). 4.3.2 stack the pic16c55x family has an 8-level deep x 13-bit wide hardware stack (figure 4-1 and figure 4-2). the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return , retlw or a ret- fie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 4.4 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf reg- ister. any instruction using the indf register actually accesses data pointed to by the file select register (fsr). reading indf itself indirectly will produce 00h. writing to the indf register indirectly results in a no- operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 4-7. however, irp is not used in the pic16c55x. a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 4-1. example 4-1: indirect addressing pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu result goto, call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions mnemonics called push or pop. these are actions that occur from the execution of the call , return, retlw and retfie instructions, or vectoring to an interrupt address. movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next ;yes continue continue:
pic16c55x ds40143e-page 22 preliminary ? 1996-2013 microchip technology inc. figure 4-7: direct/indirect addressing pic16c55x for memory map detail see figure 4-3 and figure 4-5. note 1: the rp1 and irp bits are reserved, always maintain these bits clear. data memory indirect addressing direct addressing bank select location select (1) rp1 rp0 6 0 from opcode irp (1) fsr register 7 0 bank select location select 00 01 10 11 00h 7fh 00h 7fh bank 0 bank 1 bank 2 bank 3 not used
? 1996-2013 microchip technology inc. preliminary ds40143e-page 23 pic16c55x 5.0 i/o ports the pic16c554 and pic16c558 have two ports, porta and portb. the pic16c557 has three ports, porta, portb and portc. 5.1 porta and trisa registers porta is a 5-bit wide latch. ra4 is a schmitt trigger input and an open-drain output. port ra4 is multiplexed with the t0cki clock input. all other ra port pins have schmitt trigger input levels and full cmos output driv- ers. all pins have data direction bits (tris registers) which can configure these pins as input or output. a '1' in the trisa register puts the corresponding out- put driver in a hi-impedance mode. a '0' in the trisa register puts the contents of the output latch on the selected pin(s). reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. so a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. figure 5-1: block diagram of ? port pins ra<3:0> figure 5-2: block diagram of ra4 pin note 1: on reset, the trisa register is set to all inputs. data bus q d q ck q d q ck qd en p n wr porta wr trisa data latch tris latch rd trisa rd porta schmitt input buffer v ss v dd i/o pin trigger v ss v dd data bus wr porta wr trisa rd porta data latch trisa latch rd trisa schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input q d q ck q d q ck en qd en v ss
pic16c55x ds40143e-page 24 preliminary ? 1996-2013 microchip technology inc. table 5-1: porta functions table 5-2: summary of registers associated with porta name bit # buffer type function ra0 bit 0 st bi-directional i/o port. ra1 bit 1 st bi-directional i/o port. ra2 bit 2 st bi-directional i/o port. ra3 bit 3 st bi-directional i/o port. ra4/t0cki bit 4 st bi-directional i/o port or external clock input for tmr0. output is open drain type. legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 05h porta ? ? ? ra4 ra3 ra2 ra1 ra0 ---x xxxx ---u uuuu 85h trisa ? ? ? trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 legend: ? = unimplemented locations, r ead as ?0?, x = unknown, u = unchanged note 1: shaded bits are not used by porta.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 25 pic16c55x 5.2 portb and trisb registers portb is an 8-bit wide bi-directional port. the corresponding data direction register is trisb. a '1' in the trisb register puts the corresponding output driver in a hi-impedance mode. a '0' in the trisb register puts the contents of the output latch on the selected pin(s). reading portb register reads the status of the pins whereas writing to it will write to the port latch. all write operations are read-modify-write operations. so a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. each of the portb pins has a weak internal pull-up ( ? 200 ? a typical). a single control bit can turn on all the pull-ups. this is done by clearing the rbpu (option<7>) bit. the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on power-on reset. four of portb?s pins, rb7:rb4, have an interrupt-on- change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt- on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are or?ed together to generate the rbif interrupt (flag latched in intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: ? any read or write of portb (this will end the mis- match condition) ? clear flag bit rbif a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition, and allow flag bit rbif to be cleared. the interrupt on mismatch feature, together with software configurable pull-ups on these four pins, allows easy interface to a key pad and make it possible for wake-up on key-depression. (see an552 in the microchip embedded control handbook .) the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. figure 5-3: block diagram of rb7:rb4 pins note 1: if a change on the i/o pin should occur when the read operation is being exe- cuted (start of the q2 cycle), then the rbif interrupt flag may not get set. p n v ss v dd data latch from other rbpu (1) p v dd i/o data bus wr portb wr trisb set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up rd portb latch ttl input buffer pin st buffer rb7:rb6 in serial programming mode v dd v ss q d ck q d q ck en q d en qd note 1: trisb = 1 enables weak pull-up if rbpu = ?0? (option<7>).
pic16c55x ds40143e-page 26 preliminary ? 1996-2013 microchip technology inc. figure 5-4: block diag ram of rb3:rb0 pins table 5-3: portb functions table 5-4: summary of registers as sociated with portb and trisb name bit # buffer type function rb0/int bit 0 ttl/st (1) bi-directional i/o port. internal software programmable weak pull-up. rb1 bit 1 ttl bi-directional i/o port. inter nal software programmable weak pull-up. rb2 bit 2 ttl bi-directional i/o port. inter nal software programmable weak pull-up. rb3 bit 3 ttl bi-directional i/o port. inter nal software programmable weak pull-up. rb4 bit 4 ttl bi-directional i/o port (with inte rrupt-on-change). internal software programmable weak pull-up. rb5 bit 5 ttl bi-directional i/o port (with inte rrupt-on-change). internal software programmable weak pull-up. rb6 bit 6 ttl/st (2) bi-directional i/o port (with interrupt- on-change). internal software programmable weak pull-up. serial programming clock pin. rb7 bit 7 ttl/st (2) bi-directional i/o port (with interrupt- on-change). internal software programmable weak pull-up. serial programming data pin. legend: st = schmitt trigger, ttl = ttl input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 0bh, 8bh intcon gie reserved t0ie inte brie t0if intf rbif 0000 000x 0000 000x legend: x = unknown, u = unchanged note 1: shaded bits are not used by portb. p n v ss v dd rbpu (1) p v dd i/o data bus wr portb wr trisb rd trisb rd portb weak pull-up rd portb latch ttl input buffer pin st buffer rb0/int v dd v ss st buffer en q d data latch tris latch q d ck q d q ck note 1: trisb = 1 enables weak pull-up if rbpu = ?0? (option<7>).
? 1996-2013 microchip technology inc. preliminary ds40143e-page 27 pic16c55x 5.3 portc and trisc registers (1) portc is a 8-bit wide latch. all pins have data direc- tion bits (tris registers) which can configure these pins as input or output. a '1' in the trisc register puts the corresponding out- put driver in a hi-impedance mode. a '0' in the trisc register puts the contents of the output latch on the selected pin(s). reading the portc register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. so a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch figure 5-5: block diagram of port pins rc<7:0> table 5-5: portc functions table 5-6: summary of registers as sociated with portc and trisc data bus q d q ck q d q ck qd en p n wr portc wr data latch tris latch rd trisc rd portc v ss v dd i/o pin v ss v dd trisc ttl input buffer name bit # buffer type function rc0 bit 0 ttl bi-directional i/o port. rc1 bit 1 ttl bi-directional i/o port. rc2 bit 2 ttl bi-directional i/o port. rc3 bit 3 ttl bi-directional i/o port. rc4 bit 4 ttl bi-directional i/o port. rc5 bit 5 ttl bi-directional i/o port. rc6 bit 6 ttl bi-directional i/o port. rc7 bit 7 ttl bi-directional i/o port. legend: st = schmitt trigger, ttl = ttl input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: x = unknown, u = unchanged note 1: pic16c557 only.
pic16c55x ds40143e-page 28 preliminary ? 1996-2013 microchip technology inc. 5.4 i/o programming considerations 5.4.1 bi-directional i/o ports any instruction which writes, operates internally as a read followed by a write operation. the bcf and bsf instructions, for example, read the register into the cpu, execute the bit operation and write the result back to the register. caution must be used when these instructions are applied to a port with both inputs and outputs defined. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu. then the bsf operation takes place on bit5 and portb is written to the output latches. if another bit of portb is used as a bi-directional i/o pin (e.g., bit 0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and re-written to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit 0 is switched into output mode later on, the content of the data latch may now be unknown. reading the port register, reads the values of the port pins. writing to the port register writes the value to the port latch. when using read-modify-write instructions (ex. bcf, bsf , etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. example 5-1 shows the effect of two sequential read- modify-write instructions (ex., bcf,bsf , etc.) on an ? i/o port. a pin actively outputting a low or high should not be driven from external devices at the same time in order to change the level on this pin (?wired-or?, ?wired-and?). the resulting high output currents may damage the chip.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 29 pic16c55x example 5-1: read-modify-write instructions on an ? i/o port 5.4.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle, as shown in figure 5-6. therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the cpu is executed. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with an nop or another instruction not accessing this i/o port. figure 5-6: successive i/o operation ; initial port settings: portb<7:4> inputs ; ; portb<3:0> outputs ; portb<7:6> have external pull-up and are ? ; not connected to other circuitry ; ; port latch port pins ; ---------- --------- ; bcf portb, 7 ; 01pp pppp 11pp pppp bcf portb, 6 ; 10pp pppp 11pp pppp bsf status, rp0 ; bcf trisb, 7 ; 10pp pppp 11pp pppp bcf trisb, 6 ; 10pp pppp 10pp pppp note 1: this example shows write to portb followed by a read from portb. 2: data setup time = (0.25 t cy - t pd ) where t cy = instruction cycle and t pd = propagation delay of q1 cycle to output valid. therefore, at higher clock frequencies, a write followed by a read may be problematic. q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 rb <7:0> port pin sampled here pc pc + 1 pc + 2 pc + 3 nop nop movf portb, w read portb movwf portb write to portb pc instruction fetched t pd execute movwf portb execute movf portb, w execute nop
pic16c55x ds40143e-page 30 preliminary ? 1996-2013 microchip technology inc. notes:
? 1996-2013 microchip technology inc. preliminary ds40143e-page 31 pic16c55x 6.0 special features of the cpu what sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. the pic16c55x family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. these are: 1. osc selection 2. reset 3. power-on reset (por) 4. power-up timer (pwrt) 5. oscillator start-up timer (ost) 6. interrupts 7. watchdog timer (wdt) 8. sleep 9. code protection 10. id locations 11. in-circuit serial programming? the pic16c55x has a watchdog timer which is controlled by configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), which is intended to keep the chip in reset until the crystal oscillator is sta- ble. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. with these two functions on- chip, most applications need no external reset cir- cuitry. the sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options. 6.1 configuration bits the configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. these bits are mapped in program memory location 2007h. the user will note that address 2007h is beyond ? the user program memory space. in fact, it belongs to the special test/configuration memory space (2000h ? 3fffh), which can be accessed only during programming.
pic16c55x ds40143e-page 32 preliminary ? 1996-2013 microchip technology inc. register 6-1: co nfiguration word cp1 cp0 cp1 cp0 cp1 cp0 ? reserved cp1 cp0 pwrte wdte f0sc1 f0sc0 bit 13 bit 0 bit 13-8 bit 5-4 cp<1:0> : code protection bits (1) 11 = program memory code protection off 10 = 0400h - 07ffh code protected 01 = 0200h - 07ffh code protected 11 = 0000h - 07ffh code protected bit 7 unimplemented : read as '1' bit 6 reserved: do not use bit 3 pwrte : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 2 wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0 fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: all of the cp1:cp0 pairs have to be given the same value to enable the code protection scheme listed. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1996-2013 microchip technology inc. preliminary ds40143e-page 33 pic16c55x 6.2 oscillator configurations 6.2.1 oscillator types the pic16c55x can be operated in four different oscillator options. the user can program two configuration bits (fosc1 and fosc0) to select one of these four modes: ? lp low power crystal ? xt crystal/resonator ? hs high speed crystal/resonator ? rc resistor/capacitor 6.2.2 crystal oscillator / ceramic resonators in xt, lp or hs modes a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation (figure 6-1). the pic16c55x oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1 pin (figure 6-2). figure 6-1: crystal operation ? (or ceramic resonator) (hs, xt or lp osc configuration) figure 6-2: exter nal clock input operation (hs, xt or lp osc configuration) table 6-1: capacitor selection for ceramic resonators (preliminary) table 6-2: capacitor selection for crystal oscillator (preliminary) note 1: a series resistor may be required for at strip cut crystals. 2: see table 6-1 and table 6-2 for recommended val- ues of c1 and c2. c1 c2 xtal osc2 rs osc1 rf sleep to internal logic pic16c55x note 1 clock from ext. system pic16c55x osc1 osc2 open ranges characterized: mode freq osc1(c1) osc2(c2) xt 455 khz 2.0 mhz 4.0 mhz 22 - 100 pf 15 - 68 pf 15 - 68 pf 22 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf note 1: higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for design guidance only. since each resonator has its own characteristics, the user should consult with the resonator manufacturer for appropriate values of external compo- nents. mode freq osc1(c1) osc2(c2) lp 32 khz 200 khz 68 - 100 pf 15 - 30 pf 68 - 100 pf 15 - 30 pf xt 100 khz 2 mhz 4 mhz 68 - 150 pf 15 - 30 pf 15 - 30 pf 150 - 200 pf 15 - 30 pf 15 - 30 pf hs 8 mhz 10 mhz 20 mhz 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf note 1: higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid over- driving crystals with low-drive level specifi- cation. since each crystal has its own characteristics, the user should consult with the crystal manufacturer for appropri- ate values of external components.
pic16c55x ds40143e-page 34 preliminary ? 1996-2013 microchip technology inc. 6.2.3 external crystal oscillator circuit either a pre-packaged oscillator can be used or a sim- ple oscillator circuit with ttl gates can be built. prepackaged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used: one with series resonance, or one with parallel resonance. figure 6-3 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180 ? phase shift that a parallel oscillator requires. the 4.7 k ? resistor provides the negative feedback for stability. the 10 k ? potentiometers bias the 74as04 in the linear region. this could be used for external oscillator designs. figure 6-3: external parallel resonant crystal oscillator circuit figure 6-4 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the crystal. the inverter performs a 180 ? phase shift in a series resonant oscillator circuit. the 330 ? resistors provide the negative feedback to bias the inverters in their linear region. figure 6-4: external series resonant crystal oscillator circuit 6.2.4 rc oscillator for timing insensitive applications the ?rc? device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values, and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 6-5 shows how the r/c combination is connected to the pic16c55x. for r ext values below 2.2 k ? , the oscillator operation may become unstable, or stop completely. for very high r ext values (e.g., 1 m ? ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend to keep r ext between 3 k ? and 100 k ? . although the oscillator will operate with no external capacitor (c ext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or package lead frame capacitance. the oscillator frequency, divided by 4, is available on the osc2/clkout pin, and can be used for test purposes or to synchronize other logic (figure 3-2 for waveform). figure 6-5: rc oscillator mode 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic16c55x clk in to o t h e r devices 330 ? 74as04 74as04 pic16c55x clk in to other devices xtal 330 ? 74as04 0.1 ? f osc2/clkout c ext r ext v ss pic16c55x osc1 fosc/4 internal clock v dd
? 1996-2013 microchip technology inc. preliminary ds40143e-page 35 pic16c55x 6.3 reset the pic16c55x differentiates between various kinds of reset: ? power-on reset (por) ?mclr reset during normal operation ?mclr reset during sleep ? wdt reset (normal operation) ? wdt wake-up (sleep) some registers are not affected in any reset condi- tion; their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on power-on reset, on mclr or wdt reset and on mclr reset during sleep. they are not affected by a wdt wake-up, since this is viewed as the resumption of normal operation. to and pd bits are set or cleared differently in different reset situations as indicated in table 6-4. these bits are used in software to determine the nature of the reset. see table 6-6 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 6-6. the mclr reset path has a noise filter to detect and ignore small pulses. see table 10-3 for pulse width specification. figure 6-6: simplified block di agram of on-chip reset circuit s r q external reset mclr / v dd osc1/ wdt module v dd rise detect ost/pwrt on-chip (1) rc osc wdt timeout power-on reset ost pwrt chip_reset 10-bit ripple-counter reset enable ost enable pwrt sleep see table 6-3 for timeout situations. note 1: this is a separate oscillator from the rc oscillator of the clkin pin. clkin pin v pp pin 10-bit ripple-counter
pic16c55x ds40143e-page 36 preliminary ? 1996-2013 microchip technology inc. 6.4 power-on reset (por), power-up timer (pwrt), oscillator start-up timer (ost) 6.4.1 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.6v ? 1.8v). to take advantage of the por, just tie the mclr pin through a resistor to v dd . this will eliminate external rc components usually needed to create power-on reset. a maximum rise time for v dd is required. see electrical specifications for details. the por circuit does not produce internal reset when v dd declines. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating con- ditions are met. for additional information, refer to application note an607 ?power-up trouble shooting?. 6.4.2 power-up timer (pwrt) the power-up timer provides a fixed 72 ms (nominal) timeout on power-up only, from por. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as pwrt is active. the pwrt delay allows the v dd to rise to an acceptable level. a configuration bit, pwrte can disable (if set) or enable (if cleared or programmed) the power-up timer. the power-up time delay will vary from chip to chip and due to v dd , temperature and process variation. see dc parameters for details. 6.4.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over. this ensures that the crystal oscillator or resonator has started and stabilized. the ost timeout is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 6.4.4 timeout sequence on power-up, the timeout sequence is as follows: first pwrt timeout is invoked after por has expired, then ost is activated. the total timeout will vary based on oscillator configuration and pwrte bit status. for example, in rc mode with pwrte bit erased (pwrt disabled), there will be no timeout at all. figure 6-7, figure 6-8 and figure 6-9 depict timeout sequences. since the timeouts occur from the por pulse, if mclr is kept low long enough, the timeouts will expire. then bringing mclr high will begin execution immediately (see figure 6-8). this is useful for testing purposes or to synchronize more than one pic16c55x device oper- ating in parallel. table 6-5 shows the reset conditions for some spe- cial registers, while table 6-6 shows the reset condi- tions for all the registers.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 37 pic16c55x 6.4.5 power control/status register (pcon) bit1 is por (power-on reset). it is a ?0? on power-on reset and unaffected otherwise. the user must write a ?1? to this bit following a power-on reset. on a subse- quent reset if por is ?0?, it will indicate that a power- on reset must have occurred (v dd may have gone too low). table 6-3: timeout in various situations table 6-4: status bits and their significance oscillator configuration power-up wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp 72 ms + 1024 t osc 1024 t osc 1024 t osc rc 72 ms ? ? por to pd 011 power-on reset 00x illegal, to is set on por 0x0 illegal, pd is set on por 10u wdt reset 100 wdt wake-up 1uu mclr reset during normal operation 110 mclr reset during sleep
pic16c55x ds40143e-page 38 preliminary ? 1996-2013 microchip technology inc. table 6-5: initialization condition for special registers table 6-6: initialization condition for registers condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0- mclr reset during normal operation 000h 000u uuuu ---- --u- mclr reset during sleep 000h 0001 0uuu ---- --u- wdt reset 000h 0000 uuuu ---- --u- wdt wake-up pc + 1 uuu0 0uuu ---- --u- interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --u- legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?0?, q = value depends on condition. note 1: when the wake-up is due to an interrupt and global enable bit, gie is set, the pc is loaded with the inter- rupt vector (0004h) after execution of pc+1. register address power-on reset mclr reset during normal operation mclr reset during sleep wdt reset wake-up from sleep through interrupt wake-up from sleep through wdt timeout w? xxxx xxxx uuuu uuuu uuuu uuuu indf 00h ? ? ? tmr0 01h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h 0000 0000 0000 0000 pc + 1 (2) status 03h 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 04h xxxx xxxx uuuu uuuu uuuu uuuu porta 05h ---x xxxx ---u uuuu ---u uuuu portb 06h xxxx xxxx uuuu uuuu uuuu uuuu portc (4) 06h xxxx xxxx uuuu uuuu uuuu uuuu pclath 0ah ---0 0000 ---0 0000 ---u uuuu intcon 0bh 0000 000x 0000 000u uuuu uuuu (1) option 81h 1111 1111 1111 1111 uuuu uuuu trisa 85h ---1 1111 ---1 1111 ---u uuuu trisb 86h 1111 1111 1111 1111 uuuu uuuu trisc (4) 86h 1111 1111 1111 1111 uuuu uuuu pcon 8eh ---- --0- ---- --u- ---- --u- legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?0?, q = value depends on condition. note 1: one or more bits in intcon will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 6-5 for reset value for specific condition. 4: pic16c557 only.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 39 pic16c55x figure 6-7: timeout sequence on power-up (mclr not tied to v dd ): case 1 figure 6-8: timeout sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt timeout ost timeout internal reset v dd mclr internal por pwrt timeout ost timeout internal reset t pwrt t ost
pic16c55x ds40143e-page 40 preliminary ? 1996-2013 microchip technology inc. figure 6-9: timeout sequence on power-up (mclr tied to v dd ): case 3 figure 6-10: exte rnal power-on reset circuit (for slow v dd power-up) t pwrt t ost v dd mclr internal por pwrt timeout ost timeout internal reset note 1: external power-on reset circuit is required only if v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: < 40 k ? is recommended to make sure that voltage drop across r does not violate the device?s electrical specification. 3: r1 = 100 ? to 1 k ? will limit any current flowing into mclr from external capacitor c in the event of mclr /v pp pin breakdown due to electrostatic dis- charge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic16c55x v dd
? 1996-2013 microchip technology inc. preliminary ds40143e-page 41 pic16c55x 6.5 interrupts the pic16c55x has 3 sources of interrupt: ? external interrupt rb0/int ? tmr0 overflow interrupt ? portb change interrupts (pins rb7:rb4) the interrupt control register (intcon) records individual interrupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. individual interrupts can be disabled through their corresponding enable bits in intcon register. gie is cleared on reset. the ?return from interrupt? instruction, retfie , exits the interrupt routine as well as sets the gie bit, which re-enables rb0/int interrupts. the int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. when an interrupt is responded to, the gie is cleared to disable any further interrupt, the return address is pushed into the stack and the pc is loaded with 0004h. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in soft- ware before re-enabling interrupts to avoid rb0/int recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs (figure 6-12). the latency is the same for one or two cycle instructions. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the gie bit. figure 6-11: interrupt logic note 1: individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the gie bit. 2: when an instruction that clears the gie bit is executed, any interrupts that were pending for execution in the next cycle are ignored. the cpu will execute a nop in the cycle immediately following the instruction which clears the gie bit. the interrupts which were ignored are still pending to be serviced when the gie bit is set again. rbif rbie t0if t0ie intf inte gie wake-up (if in sleep mode) interrupt to cpu
pic16c55x ds40143e-page 42 preliminary ? 1996-2013 microchip technology inc. 6.5.1 rb0/int interrupt an external interrupt on rb0/int pin is edge triggered: either rising if intedg bit (option<6>) is set, or fall- ing if intedg bit is clear. when a valid edge appears on the rb0/int pin, the intf bit (intcon<1>) is set. this interrupt can be disabled by clearing the inte control bit (intcon<4>). the intf bit must be cleared in software in the interrupt service routine before re- enabling this interrupt. the rb0/int interrupt can wake-up the processor from sleep, if the inte bit was set prior to going into sleep. the status of the gie bit decides whether or not the processor branches to the interrupt vector following wake-up. see section 6.8 for details on sleep and figure 6-14 for timing of wake- up from sleep through rb0/int interrupt. 6.5.2 tmr0 interrupt an overflow (ffh ? 00h) in the tmr0 register will set the t0if (intcon<2>) bit. the interrupt can be enabled/disabled by setting/clearing t0ie (intcon<5>) bit. for operation of the timer0 module, see section 7.0. 6.5.3 portb interrupt an input change on portb <7:4> sets the rbif (intcon<0>) bit. the interrupt can be enabled/dis- abled by setting/clearing the rbie (intcon<4>) bit. for operation of portb (section 5.2). figure 6-12: int pin interrupt timing note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the rbif inter- rupt flag may get set. q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed interrupt latency pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dummy cycle inst (pc) ? 1 4 5 1 2 3 note 1: intf flag is sampled here (every q1). 2: interrupt latency = 3-4 t cy where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout is available only in rc oscillator mode. 4: for minimum width of int pulse, refer to ac specs. 5: intf is enabled to be set anytime during the q4-q1 cycles.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 43 pic16c55x 6.6 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt (e.g., w register and status register). this will have to be implemented in software. example 6-1 stores and restores the status and w registers. the user register, w_temp , must be defined in both banks and must be defined at the same offset from the bank base address (i.e., w_temp is defined at 0x20 in bank 0 and it must also be defined at 0xa0 in bank 1). the user register, status_temp , must be defined in bank 0. the example 6-1: ? stores the w register ? stores the status register in bank 0 ? executes the isr code ? restores the status (and bank select bit ? register) ? restores the w register example 6-1: saving the status and w registers in ram 6.7 watchdog timer (wdt) the watchdog timer is a free running on-chip rc oscil- lator which does not require any external components. this rc oscillator is separate from the rc oscillator of the clkin pin. that means that the wdt will run, even if the clock on the osc1 and osc2 pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt timeout generates a device reset. if the device is in sleep mode, a wdt timeout causes the device to wake-up and continue with normal operation. the wdt can be permanently disabled by programming the con- figuration bit wdte as clear (section 6.1). 6.7.1 wdt period the wdt has a nominal timeout period of 18 ms, (with no prescaler). the timeout periods vary with tempera- ture, v dd and process variations from part-to-part (see dc specs). if longer timeout periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt under software control by writing to the option register. thus, timeout periods up to 2.3 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset. the to bit in the status register will be cleared upon a watchdog timer timeout. 6.7.2 wdt programming considerations it should also be taken in account that under worst case conditions (v dd = min., temperature = max., max. wdt prescaler) it may take several seconds before a wdt timeout occurs. movwf w_temp ;copy w to temp ;register, could be in ;either bank swapf status,w ;swap status to be ;saved into w bcf status,rp0 ;change to bank0 ? ;regardless of ;current bank movwf status_temp ;save status to bank0 ;register : : : swapf status_temp,w;swap status_temp ? ;register into w, sets ? ;bank to original state movwf status ;move w into status ? ;register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
pic16c55x ds40143e-page 44 preliminary ? 1996-2013 microchip technology inc. figure 6-13: watchdog timer block diagram table 6-7: summary of watchdog timer registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 2007h config. bits ? reserved cp1 cp0 pwrte wdte fosc1 fosc0 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, q = value depends on condition, ? = unimplemented, read as ?0?. ? shaded cells are not used by the watchdog timer. postscaler m u x note 1: t0se, t0cs, psa, ps0-ps2 are bits in the option register. from tmr0 clock source (figure 7-6) watchdog timer wdt enable bit 0 1 psa 8 - to - 1 mux 8 ps<2:0> to t m r 0 (figure 7-6) 01 psa wdt timeout mux
? 1996-2013 microchip technology inc. preliminary ds40143e-page 45 pic16c55x 6.8 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit in the status register is cleared, the to bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had, before sleep was executed (driving high, low, or hi- impedance). for lowest current consumption in this mode, all i/o pins should be either at v dd , or v ss , with no external circuitry drawing current from the i/o pin. i/o pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by float- ing inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). 6.8.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin 2. watchdog timer wake-up (if wdt was enabled) 3. interrupt from rb0/int pin or rb port change the first event will cause a device reset. the two lat- ter events are considered a continuation of program execution. the to and pd bits in the status register can be used to determine the cause of device reset. pd bit, which is set on power-up is cleared when sleep is invoked. to bit is cleared if wdt wake-up occurred. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the correspond- ing interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have an nop after the sleep instruction. the wdt is cleared when the device wakes-up from sleep, regardless of the source of wake-up. figure 6-14: wake-up from sleep through interrupt note: it should be noted that a reset generated by a wdt timeout does not drive mclr pin low. note: if the global interrupts are disabled (gie is cleared), but any interrupt source has both its interrupt enable bit and the correspond- ing interrupt flag bits set, the device will immediately wake-up from sleep. the sleep instruction is completely executed. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale). this delay will not be there for rc osc mode. 3: gie = '1' assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = '0', execution will cont inue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference.
pic16c55x ds40143e-page 46 preliminary ? 1996-2013 microchip technology inc. 6.9 code protection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. 6.10 id locations four memory locations (2000h-2003h) are designated as id locations where the user can store checksum or other code-identification numbers. these locations are not accessible during normal execution but are readable and writable during program/verify. 6.11 in-circuit serial programming? the pic16c55x microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. the device is placed into a program/verify mode by holding the rb6 and rb7 pins low while raising the mclr (v pp ) pin from v il to v ihh (see programming specification). rb6 becomes the programming clock and rb7 becomes the programming data. both rb6 and rb7 are schmitt trigger inputs in this mode. after reset, to place the device into programming/ verify mode, the program counter (pc) is at location 00h. a 6-bit command is then supplied to the device. depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a load or a read. for complete details of serial programming, please refer to the pic16c6x/7x programming specifications (literature #ds30228). a typical in-circuit serial programming connection is shown in figure 6-15. figure 6-15: typical in-circuit serial programming connection note: microchip does not recommend code protecting windowed devices. external connector signals to n o r m a l connections to n o r m a l connections pic16c55x v dd v ss mclr /v pp rb6 rb7 +5v 0v v pp clk data i/o v dd
? 1996-2013 microchip technology inc. preliminary ds40143e-page 47 pic16c55x 7.0 timer0 module the timer0 module timer/counter has the following features: ? 8-bit timer/counter ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select ? interrupt on overflow from ffh to 00h ? edge select for external clock figure 7-1 is a simplified block diagram of the timer0 module. timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the tmr0 will increment every instruction cycle (without prescaler). if timer0 is written, the increment is inhibited for the following two cycles (figure 7-2 and figure 7-3). the user can work around this by writing an adjusted value to tmr0. counter mode is selected by setting the t0cs bit. in this mode timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the source edge (t0se) control bit (option<4>). clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed in detail in section 7.2. the prescaler is shared between the timer0 module and the watchdog timer. the prescaler assignment is controlled in software by the control bit psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale value of 1:2, 1:4, ..., 1:256 are selectable. section 7.3 details the operation of the prescaler. 7.1 timer0 interrupt timer0 interrupt is generated when the tmr0 register timer/counter overflows from ffh to 00h. this overflow sets the t0if bit. the interrupt can be masked by clearing the t0ie bit (intcon<5>). the t0if bit (intcon<2>) must be cleared in software by the timer0 module interrupt service routine before re- enabling this interrupt. the timer0 interrupt cannot wake the processor from sleep since the timer is shut off during sleep. see figure 7-4 for timer0 interrupt timing. figure 7-1: timer0 block diagram figure 7-2: timer0 (tmr 0) timing: internal cl ock/no prescaler note 1: bits, t0se, t0cs, ps2, ps1, ps0 and psa are located in the option register. 2: the prescaler is shared with watchdog timer (figure 7-6) ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 psout (2 tcy delay) psout data bus 8 set flag bit t0if on overflow psa ps2:ps0 pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 t0 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed
pic16c55x ds40143e-page 48 preliminary ? 1996-2013 microchip technology inc. figure 7-3: timer0 timing: internal clock/prescale 1:2 figure 7-4: timer0 interrupt timing pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 1 1 osc1 clkout(3) tmr0 timer t0if bit (intcon<2>) feh gie bit (intcon<7>) instruction flow pc instruction fetched pc pc +1 pc +1 0004h 0005h instruction executed inst (pc) inst (pc-1) inst (pc+1) inst (pc) inst (0004h) inst (0005h) inst (0004h) dummy cycle dummy cycle ffh 00h 01h 02h interrupt latency time note 1: t0if interrupt flag is sampled here (every q1). 2: interrupt latency = 4 t cy , where t cy = instruction cycle time. 3: clkout is available only in rc oscillator mode.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 49 pic16c55x 7.2 using timer0 with external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock requirement is due to internal phase clock (t osc ) synchronization. also, there is a delay in the actual incrementing of timer0 after synchronization. 7.2.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 7-5). therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. therefore, it is necessary for t0cki to have a period of at least 4t osc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the minimum pulse width requirement of 10 ns. refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 7.2.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the tmr0 is actually incremented. figure 7-5 shows the delay from the external clock edge to the timer incrementing. figure 7-5: timer0 timing with external clock 7.3 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer, respectively (figure 7-6). for simplicity, this counter is being referred to as ?prescaler? throughout this data sheet. the psa and ps2:ps0 bits (option<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the prescaler is not readable or writable. q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 external clock input or prescaler output (2) external clock/prescaler output after sampling increment timer0 (q4) timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling (3) (1) note 1: delay from clock input change to timer0 increment is 3 t osc to 7 t osc . (duration of q = t osc ). therefore, the error in measuring the interval between two edges on timer0 input = 4 t osc max. 2: external clock if no prescaler selected, prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs. note: there is only one prescaler available which is mutually exclusive between the timer0 module and the watchdog timer. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer, and vice-versa.
pic16c55x ds40143e-page 50 preliminary ? 1996-2013 microchip technology inc. figure 7-6: block diag ram of the timer0/wdt prescaler t0cki t0se pin m u x clkout (=fosc/4) sync 2 tc y tmr0 reg 8-bit prescaler 8-to-1mux m u x m u x watchdog timer psa 01 0 1 wdt timeout ps0 - ps2 8 psa wdt enable bit m u x 0 1 0 1 data bus set flag bit t0if on overflow 8 psa t0cs note 1: t0se, t0cs, psa, ps0-ps2 are bits in the option register.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 51 pic16c55x 7.3.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on the fly? during program execution). to avoid an unintended device reset, the following instruction sequence (example 7-1) must be executed when changing the prescaler assignment from timer0 to wdt. lines 5-7 are required only if the desired postscaler rate is 1:1 (ps<2:0> = 000) or 1:2 (ps<2:0> = 001). example 7-1: changing prescaler (timer0 ? wdt) to change prescaler from the wdt to the tmr0 module use the sequence shown in example 7-2. this precaution must be taken even if the wdt is disabled. example 7-2: changing prescaler (wdt ? timer0) table 7-1: registers associated with timer0 bcf status, rp0 ;skip if already in ? ;bank 0 clrwdt clear wdt clrf tmr0 ;clear tmr0 & prescaler bsf status, rp0 ;bank 1 movlw '00101111?b ;these 3 lines (5, 6, 7) movwf option ;are required only if ;desired ps<2:0> are ;clrwdt 000 or 001 movlw '00101xxx?b ;set postscaler to movwf option ;desired wdt rate bcf status, rp0 ;return to bank 0 clrwdt ;clear wdt and ? ;prescaler bsf status, rp0 movlw b'xxxx0xxx' ;select tmr0, new ? ;prescale value and ? ;clock source movwf option bcf status, rp0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets 01h tmr0 timer0 module?s register xxxx xxxx uuuu uuuu 0bh/8bh intcon gie reserved t0ie inte rbie t0if intf rbif 0000 000x 0000 000x 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa ? ? ? trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 legend: ? = unimplemented locations, read as ?0?, note 1: shaded bits are not used by tmr0 module.
pic16c55x ds40143e-page 52 preliminary ? 1996-2013 microchip technology inc. notes:
? 1996-2013 microchip technology inc. preliminary ds40143e-page 53 pic16c55x 8.0 instruction set summary each pic16c55x instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. the pic16c55x instruc- tion set summary in table 8-2 lists byte-oriented , bit- oriented , and literal and control operations. table 8- 1 shows the opcode field descriptions. for byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 8-1: opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations all instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop . one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 ? s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 ? s. table 8-1 lists the instructions recognized by the mpasm? assembler. figure 8-1 shows the three general formats that the instructions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 8-1: general format for instructions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1 ) the assembler will generate code with x = 0 . it is the recommended form of use for compatibil- ity with all microchip software tools. d destination select; d = 0 : store result in w, d = 1 : store result in file register f. default is d = 1 label label name tos top of stack pc program counter pclath program counter high latch gie global interrupt enable bit wdt watchdog timer/counter to timeout bit pd power-down bit dest destination either the w register or the specified register file location [ ] options ( ) contents ? assigned to < > register bit field ? in the set of italics user defined term (font is courier) note: to maintain upward compatibility with future pic ? mcu products, do not use the option and tris instructions. byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16c55x ds40143e-page 54 preliminary ? 1996-2013 microchip technology inc. table 8-2: pic16c55x instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1(2) 1(2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to ,pd z to ,pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register ( and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop .
? 1996-2013 microchip technology inc. preliminary ds40143e-page 55 pic16c55x 8.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z encoding: 11 111x kkkk kkkk description: the contents of the w register are added to the eight bit literal 'k' and the result is placed in the w register. words: 1 cycles: 1 example addlw 0x15 before instruction w = 0x10 after instruction w = 0x25 addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ??????? operation: (w) + (f) ? (dest) status affected: c, dc, z encoding: 00 0111 dfff ffff description: add the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w=0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z encoding: 11 1001 kkkk kkkk description: the contents of w register are and?ed with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example andlw 0x5f before instruction w=0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ??????? operation: (w) .and. (f) ? (dest) status affected: z encoding: 00 0101 dfff ffff description: and the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example andwf fsr, 1 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x17 fsr = 0x02
pic16c55x ds40143e-page 56 preliminary ? 1996-2013 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none encoding: 01 00bb bfff ffff description: bit 'b' in register 'f' is cleared. words: 1 cycles: 1 example bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none encoding: 01 01bb bfff ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 example bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none encoding: 01 10bb bfff ffff description: if bit 'b' in register 'f' is '0' then the next instruction is skipped. if bit 'b' is '0' then the next instruction fetched during the current instruction execution is dis- carded, and a nop is executed instead, making this a two-cycle instruction. words: 1 cycles: 1(2) example here false true btfsc goto ? ? ? flag,1 process_code before instruction pc = address here after instruction if flag<1> = 0, ? pc = address true if flag<1> = 1, ? pc = address false
? 1996-2013 microchip technology inc. preliminary ds40143e-page 57 pic16c55x btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none encoding: 01 11bb bfff ffff description: if bit 'b' in register 'f' is '1' then the next instruction is skipped. if bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and a nop is executed instead, making this a two- cycle instruction. words: 1 cycles: 1(2) example here false true btfss goto ? ? ? flag,1 process_code before instruction pc = address her e after instruction if flag<1> = 0, ? pc = address false if flag<1> = 1, ? pc = address true call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none encoding: 10 0kkk kkkk kkkk description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruc- tion. words: 1 cycles: 2 example here call there before instruction pc = address here after instruction pc = address there tos = address here+1 clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z encoding: 00 0001 1fff ffff description: the contents of register 'f' are cleared and the z bit is set. words: 1 cycles: 1 example clrf flag_reg before instruction flag_reg=0x5a after instruction flag_reg=0x00 z=1
pic16c55x ds40143e-page 58 preliminary ? 1996-2013 microchip technology inc. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z encoding: 00 0001 0000 0011 description: w register is cleared. zero bit (z) is set. words: 1 cycles: 1 example clrw before instruction w = 0x5a after instruction w = 0x00 z=1 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd encoding: 00 0000 0110 0100 description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set. words: 1 cycles: 1 example clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescaler = 0 to =1 pd =1 comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f ) ? (dest) status affected: z encoding: 00 1001 dfff ffff description: the contents of register 'f' are complemented. if 'd' is 0 the result is stored in w. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w=0xec decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) - 1 ? (dest) status affected: z encoding: 00 0011 dfff ffff description: decrement register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1
? 1996-2013 microchip technology inc. preliminary ds40143e-page 59 pic16c55x decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) - 1 ? (dest); skip if result = 0 status affected: none encoding: 00 1011 dfff ffff description: the contents of register 'f' are decremented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruction, which is already fetched, is discarded. a nop is executed instead making it a two-cycle instruction. words: 1 cycles: 1(2) example here decfsz cnt, 1 goto loop continue ? ? ? before instruction pc = address here after instruction cnt = cnt - 1 if cnt = 0, pc = address continue if cnt ? 0, pc = address here+1 goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none encoding: 10 1kkk kkkk kkkk description: goto is an unconditional branch. the eleven bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two-cycle instruction. words: 1 cycles: 2 example goto there after instruction pc = address there incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) + 1 ? (dest) status affected: z encoding: 00 1010 dfff ffff description: the contents of register 'f' are incremented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1
pic16c55x ds40143e-page 60 preliminary ? 1996-2013 microchip technology inc. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) + 1 ? (dest), skip if result = 0 status affected: none encoding: 00 1111 dfff ffff description: the contents of register 'f' are incremented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruction, which is already fetched, is discarded. a nop is executed instead making it a two-cycle instruction. words: 1 cycles: 1(2) example here incfsz cnt, 1 goto loop continue ? ? ? before instruction pc = address here after instruction cnt = cnt + 1 if cnt = 0, pc = address continue if cnt ? 0, pc = address here +1 iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z encoding: 11 1000 kkkk kkkk description: the contents of the w register is or?ed with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example iorlw 0x35 before instruction w = 0x9a after instruction w=0xbf z=1 iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (w) .or. (f) ? (dest) status affected: z encoding: 00 0100 dfff ffff description: inclusive or the w register with register 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example iorwf result, 0 before instruction result = 0x13 w=0x91 after instruction result = 0x13 w=0x93 z=1 movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none encoding: 11 00xx kkkk kkkk description: the eight bit literal 'k' is loaded into w register. the don?t cares will assemble as 0?s. words: 1 cycles: 1 example movlw 0x5a after instruction w = 0x5a
? 1996-2013 microchip technology inc. preliminary ds40143e-page 61 pic16c55x movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f) ? (dest) status affected: z encoding: 00 1000 dfff ffff description: the contents of register f is moved to a destination dependant upon the status of d. if d = 0, des- tination is w register. if d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example movf fsr, 0 after instruction w = value in fsr register z= 1 movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none encoding: 00 0000 1fff ffff description: move data from w register to register 'f'. words: 1 cycles: 1 example movwf option before instruction option = 0xff w = 0x4f after instruction option = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 00 0000 0xx0 0000 description: no operation. words: 1 cycles: 1 example nop option load option register syntax: [ label ] option operands: none operation: (w) ? option status affected: none encoding: 00 0000 0110 0010 description: the contents of the w register are loaded in the option register. this instruction is supported for code compatibility with pic16c5x products. since option is a readable/writable register, the user can directly address it. words: 1 cycles: 1 example to maintain upward compatibility with future pic mcu products, do not use this instruction.
pic16c55x ds40143e-page 62 preliminary ? 1996-2013 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none encoding: 00 0000 0000 1001 description: return from interrupt. stack is poped and top of stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a two-cycle instruction. words: 1 cycles: 2 example retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none encoding: 11 01xx kkkk kkkk description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example table call table;w contains table ;offset value ?; w now has table value ? ? addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; ? ? ? retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none encoding: 00 0000 0000 1000 description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. words: 1 cycles: 2 example return after interrupt pc = tos rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1101 dfff ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 example rlf reg1,0 before instruction reg1 = 1110 0110 c =0 after instruction reg1 = 1110 0110 w = 1100 1100 c =1 register f c
? 1996-2013 microchip technology inc. preliminary ds40143e-page 63 pic16c55x rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1100 dfff ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f' . words: 1 cycles: 1 example rrf reg1,0 before instruction reg1 = 1110 0110 c =0 after instruction reg1 = 1110 0110 w = 0111 0011 c =0 sleep syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd encoding: 00 0000 0110 0011 description: the power-down status bit, pd is cleared. timeout status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 6.8 for more details. words: 1 cycles: 1 example: sleep register f c sublw subtract w from literal syntax: [ label ] sublw k operands: 0 ?? k ?? 255 operation: k - (w) ??? w) status affected: c, dc, z encoding: 11 110x kkkk kkkk description: the w register is subtracted (2?s com- plement method) from the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example 1: sublw 0x02 before instruction w=1 c=? after instruction w=1 c = 1; result is positive example 2: before instruction w=2 c=? after instruction w=0 c = 1; result is zero example 3: before instruction w=3 c=? after instruction w=0xff c = 0; result is nega- tive
pic16c55x ds40143e-page 64 preliminary ? 1996-2013 microchip technology inc. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 127 d ? [0,1] operation: (f) - (w) ??? dest) status affected: c, dc, z encoding: 00 0010 dfff ffff description: subtract (2?s complement method) w register from register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example 1: subwf reg1,1 before instruction reg1 = 3 w=2 c=? after instruction reg1 = 1 w=2 c = 1; result is positive example 2: before instruction reg1 = 2 w=2 c=? after instruction reg1 = 0 w=2 c = 1; result is zero example 3: before instruction reg1 = 1 w=2 c=? after instruction reg1 = 0xff w=2 c = 0; result is negative swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (f<3:0>) ? (dest<7:4>), (f<7:4>) ? (dest<3:0>) status affected: none encoding: 00 1110 dfff ffff description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0 the result is placed in w register. if 'd' is 1 the result is placed in register 'f'. words: 1 cycles: 1 example swapf reg, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: 5 ? f ? 7 operation: (w) ? tris register f; status affected: none encoding: 00 0000 0110 0fff description: the instruction is supported for code compatibility with the pic16c5x products. since tris registers are readable and writable, the user can directly address them. words: 1 cycles: 1 example to maintain upward compatibility with future pic mcu products, do not use this instruction.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 65 pic16c55x xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z encoding: 11 1010 kkkk kkkk description: the contents of the w register are xor?ed with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example: xorlw 0xaf before instruction w=0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [0,1] operation: (w) .xor. (f) ??? dest) status affected: z encoding: 00 0110 dfff ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example xorwf reg 1 before instruction reg = 0xaf w=0xb5 after instruction reg = 0x1a w=0xb5
pic16c55x ds40143e-page 66 preliminary ? 1996-2013 microchip technology inc. notes:
? 1996-2013 microchip technology inc. preliminary ds40143e-page 67 pic16c55x 9.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ ? mplib tm object librarian ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - icepic? in-circuit emulator ? in-circuit debugger - mplab icd ? device programmers -pro mate ? ii universal device programmer - picstart ? plus entry-level development ? programmer ? low cost demonstration boards - picdem tm 1 demonstration board - picdem 2 demonstration board - picdem 3 demonstration board - picdem 17 demonstration board -k ee l oq ? demonstration board 9.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. the mplab ide is a windows ? -based application that contains: ? an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor ? a project manager ? customizable toolbar and key mapping ? a status bar ? on-line help the mplab ide allows you to: ? edit your source files (either assembly or ?c?) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (auto- matically updates all project information) ? debug using: - source files - absolute listing file - machine code the ability to use mplab ide with multiple debugging tools allows users to easily switch from the cost- effective simulator to a full-featured emulator with minimal retraining. 9.2 mpasm assembler the mpasm assembler is a full-featured universal macro assembler for all pic mcus. the mpasm assembler has a command line interface and a windows shell. it can be used as a stand-alone application on a windows 3.x or greater system, or it can be used through mplab ide. the mpasm assem- bler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, an abso- lute lst file that contains source lines and generated machine code, and a cod file for debugging. the mpasm assembler features include: ? integration into mplab ide projects. ? user-defined macros to streamline assembly code. ? conditional assembly for multi-purpose source files. ? directives that allow complete control over the assembly process. 9.3 mplab c17 and mplab c18 ? c compilers the mplab c17 and mplab c18 code development systems are complete ansi ?c? compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic16c55x ds40143e-page 68 preliminary ? 1996-2013 microchip technology inc. 9.4 mplink object linker/ ? mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can also link relocatable objects from pre-compiled libraries, using directives from a linker script. the mplib object librarian is a librarian for pre- compiled code to be used with the mplink object linker. when a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the mplib object librarian manages the creation and modification of library files. the mplink object linker features include: ? integration with mpasm assembler and mplab c17 and mplab c18 c compilers. ? allows all memory areas to be defined as sections to provide link-time flexibility. the mplib object librarian features include: ? easier linking because single libraries can be included instead of many smaller files. ? helps keep code maintainable by grouping related modules together. ? allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. 9.5 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc-hosted environment by simulating the pic series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. the execu- tion can be performed in single step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and the mplab c18 c compilers and the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi-project software development tool. 9.6 mplab ice high performance universal in-circuit emulator with mplab ide the mplab ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic micro- controllers (mcus). software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment (ide), which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily re configured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. the pc platform and microsoft ? windows environment were chosen to best make these features available to you, the end user. 9.7 icepic in-circuit emulator the icepic low cost, in-circuit emulator is a solution for the microchip technology pic16c5x, pic16c6x, pic16c7x and pic16cxxx families of 8-bit one- time-programmable (otp) microcontrollers. the mod- ular system can support different subsets of pic16c5x or pic16cxxx products through the use of inter- changeable personality modules, or daughter boards. the emulator is capable of emulating without target application circuitry being present.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 69 pic16c55x 9.8 mplab icd in-circuit debugger microchip's in-circuit debugger, mplab icd, is a pow- erful, low cost, run-time development tool. this tool is based on the flash pic mcus and can be used to develop for this and other pic microcontrollers. the mplab icd utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip's in-circuit serial programming tm protocol, offers cost-effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. 9.9 pro mate ii universal device programmer the pro mate ii universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as pc-hosted mode. the pro mate ii device programmer is ce compliant. the pro mate ii device programmer has program- mable v dd and v pp supplies, which allow it to verify programmed memory at v dd min and v dd max for max- imum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, or program pic devices. it can also set code protection in this mode. 9.10 picstart plus entry level development programmer the picstart plus development programmer is an easy-to-use, low cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer sup- ports all pic devices with up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 9.11 picdem 1 low cost pic mcu ? demonstration board the picdem 1 demonstration board is a simple board which demonstrates the capabilities of several of microchip?s microcontrollers. the microcontrollers sup- ported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the user can program the sample microcon- trollers provided with the picdem 1 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the user can also connect the picdem 1 demonstration board to the mplab ice in- circuit emulator and download the firmware to the emu- lator for testing. a prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simu- lated analog input, push button switches and eight leds connected to portb. 9.12 picdem 2 low cost pic16cxx demonstration board the picdem 2 demonstration board is a simple dem- onstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and soft- ware is included to run the basic demonstration pro- grams. the user can program the sample microcontrollers provided with the picdem 2 demon- stration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 2 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding additional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a serial eeprom to demonstrate usage of the i 2 c tm bus and separate headers for connection to an lcd module and a keypad.
pic16c55x ds40143e-page 70 preliminary ? 1996-2013 microchip technology inc. 9.13 picdem 3 low cost pic16cxxx demonstration board the picdem 3 demonstration board is a simple dem- onstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with an lcd mod- ule. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers pro- vided with the picdem 3 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer with an adapter socket, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 3 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem 3 demonstration board is a lcd panel, with 4 commons and 12 segments, that is capable of display- ing time, temperature and day of the week. the picdem 3 demonstration board provides an additional rs-232 interface and windows software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. 9.14 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. all neces- sary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. a programmed sample is included and the user may erase it and program it with the other sample programs using the pro mate ii device programmer, or the picstart plus development programmer, and easily debug and test the sample code. in addition, the picdem 17 dem- onstration board supports downloading of programs to and executing out of external flash memory on board. the picdem 17 demonstration board is also usable with the mplab ice in-circuit emulator, or the picmaster emulator and all of the sample programs can be run and modified using either emulator. addition- ally, a generous prototype area is available for user hardware. 9.15 k ee l oq evaluation and ? programming tools k ee l oq evaluation and programming tools support microchip?s hcs secure data products. the hcs eval- uation kit includes a lcd display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 71 pic16c55x table 9-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 pic18fxxx 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment ??????????????? mplab ? c17 c compiler ?? mplab ? c18 c compiler ?? mpasm tm assembler/ ? mplink tm object linker ??????????????? ? ? emulators mplab ? ice in-circuit emulator ??? ? ?? ** ????????? icepic tm in-circuit emulator ? ??? ??? ? debugger mplab ? icd in-circuit debugger ? * ? * ?? programmers picstart ? plus entry level development programmer ??? ? ?? ** ????????? pro mate ? ii ? universal device programmer ??? ? ?? ** ????????? ? ? demo boards and eval kits picdem tm 1 demonstration board ??? ? ?? picdem tm 2 demonstration board ? ? ? ? ?? picdem tm 3 demonstration board ? picdem tm 14a demonstration board ? picdem tm 17 demonstration board ? k ee l oq ? evaluation kit ? k ee l oq ? transponder kit ? microid tm programmer?s kit ? 125 khz microid tm ? developer?s kit ? 125 khz anticollision microid tm developer?s kit ? 13.56 mhz anticollision ? microid tm developer?s kit ? mcp2510 can developer?s kit ? * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77. ** contact microchip technology inc. for availability date. ?
pic16c55x ds40143e-page 72 preliminary ? 1996-2013 microchip technology inc. notes:
? 1996-2013 microchip technology inc. preliminary ds40143e-page 73 pic16c55x 10.0 electrical specifications absolute maximum ratings ? ambient temperature under bias ................................................................................................. ..............-40 ?? to +125 ? c storage temperature ............................................................................................................ .................... -65 ? to +150 ? c voltage on any pin with respect to v ss (except v dd and mclr ) .......................................................-0.6v to v dd +0.6v voltage on v dd with respect to v ss ................................................................................................................. 0 to +7.5v voltage on mclr with respect to v ss ................................................................................................................0 to +14v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ..........................................................................................................................3 00 ma maximum current into v dd pin ........................................................................................................................... ..250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ........................................................................................................20 ma output clamp current, i ok (v0 < 0 or v0 > v dd ).................................................................................................. 20 ma maximum output current sunk by any i/o pin ..................................................................................... ...................25 ma maximum output current sourced by any i/o pin.................................................................................. .................25 ma maximum current sunk by porta, portb and portc ................................................................................. ...200 ma maximum current sourced by porta, portb and portc .............................................................................. .200 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c55x ds40143e-page 74 preliminary ? 1996-2013 microchip technology inc. figure 10-1: voltage-frequency graph, 0 ? c ? t a ? +70 ? c (commercial temps) figure 10-2: voltage-frequency graph, ? -40 ? c ? t a ? 0 ? c, +70 ? c ? t a ? +125 ? c (outside of commercial temps) 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts. 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 75 pic16c55x figure 10-3: voltage-frequency graph, 0 ? c ? t a ? +85 ? c figure 10-4: pic16lc554/557/558 voltage-frequency graph, -40 ? c ? t a ? 0 ? c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts. 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts. 2.7
pic16c55x ds40143e-page 76 preliminary ? 1996-2013 microchip technology inc. 10.1 dc characteristics: pic16c55x-04 (commercial, industrial, extended) ? pic16c55x-20 (commercial, industrial, extended) ? hcs1365-04 (commercial, industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 ? c ? t a ? +85 ? c for industrial and 0 ? c ? t a ? +70 ? c for commercial and -40 ? c ? t a ? +125 ? c for extended param no. sym characteristic min typ? max units conditions v dd supply voltage d001 16lc55x 3.0 2.5 ?5.5 5.5 v xt and rc osc configuration lp osc configuration d001 d001a 16c55x 3.0 4.5 ? ? 5.5 5.5 v v xt, rc and lp osc configuration hs osc configuration d002 v dr ram data retention voltage (1) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?v ss ? v see section 6.4, power-on reset for details d004 s vdd v dd rise rate to ensure ? power-on reset 0.05* ? ? v/ms see section 6.4, power-on reset for details i dd supply current (2) d010 d010a 16lc55x ? ? 1.4 26 2.5 53 ma ? a xt and rc osc configuration ? fosc = 2.0 mhz, v dd = 3.0v, wdt disabled (4) lp osc configuration ? fosc = 32 khz, v dd = 3.0v, wdt disabled d010 d010a d013 16c55x ? ? ? 1.8 35 9.0 3.3 70 20 ma ? a ma xt and rc osc configuration f osc = 4 mhz, v dd = 5.5v, ? wdt disabled (4) lp osc configuration, ? pic16c55x-04 only f osc = 32 khz, v dd = 4.0v, ? wdt disabled hs osc configuration f osc = 20 mhz, v dd = 5.5v, ? wdt disabled * these parameters are characterized but not tested. ? data is ?typ? column is at 5v, 25 ? c, ? unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. ? the test conditions for all i dd measurements in active operation mode are: ? osc1 = external square wave, from rail to rail; all i/o pins configured as input, pulled to v dd , ? mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins configured as input and tied to v dd or v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2r ext (ma) with r ext in k ?? 5: the ?? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 77 pic16c55x d020 i pd power-down current (3) 16lc55x ? 0.7 2 ? av dd = 3.0v, wdt disabled 16c55x ? 1.0 2.5 15 ? a ? a v dd = 4.0v, wdt disabled (+85 ? c to +125 ? c) ? i wdt wdt current (5) 16lc55x ? 6.0 15 ? av dd = 3.0v 16c55x ? 6.0 20 ? a v dd = 4.0v (+85 ? c to +125 ? c) 10.1 dc characteristics: pic16c55x-04 (commercial, industrial, extended) ? pic16c55x-20 (commercial, industrial, extended) ? hcs1365-04 (commercial, industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 ? c ? t a ? +85 ? c for industrial and 0 ? c ? t a ? +70 ? c for commercial and -40 ? c ? t a ? +125 ? c for extended param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data is ?typ? column is at 5v, 25 ? c, ? unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. ? the test conditions for all i dd measurements in active operation mode are: ? osc1 = external square wave, from rail to rail; all i/o pins configured as input, pulled to v dd , ? mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins configured as input and tied to v dd or v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2r ext (ma) with r ext in k ?? 5: the ?? current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
pic16c55x ds40143e-page 78 preliminary ? 1996-2013 microchip technology inc. 10.2 dc characteristics: pic16c55x (commercial, industrial, extended) ? pic16lc55x(commercial, industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? ta ? +85c for industrial and 0c ? ta ? +70c for commercial and -40c ? ta ? +125c for automotive operating voltage v dd range as described in dc spec table 10-1 param. no. sym characteristic min typ? max unit conditions v il input low voltage i/o ports d030 with ttl buffer v ss ?0.8v 0.15 v dd vv dd = 4.5v to 5.5v otherwise d031 with schmitt trigger input v ss 0.2 v dd v d032 mclr , ra4/t0cki,osc1 (in rc mode) v ss ? 0.2 v dd v (note1) d033 osc1 (in xt* and hs) v ss ? 0.3 v dd v osc1 (in lp*) v ss ? 0.6 v dd -1.0 v v ih input high voltage i/o ports ? d040 with ttl buffer 2.0v 0.8 + 0.25 v dd ? ? v dd v dd v v v dd = 4.5v to 5.5v otherwise d041 with schmitt trigger input 0.8v v dd d042 mclr ra4/t0cki 0.8 v dd ?v dd v d043 d043a osc1 (xt*, hs and lp*) osc1 (in rc mode) 0.7 v dd 0.9 v dd ?v dd v (note1) d070 i purb portb weak pull-up current 50 200 400 ? a v dd = 5.0v, v pin = v ss i il input leakage current (2)(3) i/o ports (except porta) ? 1.0 ? a v ss ? v pin ? v dd , pin at hi- impedance d060 porta ? ? ? 0.5 ? a vss ?? v pin ?? v dd , pin at hi- impedance d061 ra4/t0cki ? ? ? 1.0 ? a vss ?? v pin ?? v dd d063 osc1, mclr ?? ? 5.0 ? a vss ?? v pin ?? v dd , xt, hs and lp osc configuration v ol output low voltage d080 i/o ports ? ? 0.6 v i ol =8.5 ma, v dd =4.5v, -40 ? to +85 ? c ??0.6vi ol =7.0 ma, v dd =4.5v, +125 ? c d083 osc2/clkout ? ? 0.6 v i ol =1.6 ma, v dd =4.5v, -40 ? to +85 ? c (rc only) ? ? 0.6 v i ol =1.2 ma, v dd =4.5v, +125 ? c v oh output high voltage (3) d090 i/o ports (except ra4) v dd -0.7 ? ? v i oh =-3.0 ma, v dd =4.5v, -40 ? to +85 ? c * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1 pin is a schmitt trigger input. it is not recommended that the pic16c55x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on applied voltage level. the specified levels represent nor- mal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 79 pic16c55x v dd -0.7 ? ? v i oh =-2.5 ma, v dd =4.5v, +125 ? c d092 osc2/clkout v dd -0.7 ? ? v i oh =-1.3 ma, v dd =4.5v, -40 ? to +85 ? c (rc only) v dd -0.7 ? ? v i oh =-1.0 ma, v dd =4.5v, +125 ? c * v od open-drain high voltage 10* v ra4 pin capacitive loading specs on output pins d100 cosc 2 osc2 pin 15 pf in xt, hs and lp modes when external clock used to drive osc1. d101 c io all i/o pins/osc2 (in rc mode) 50 pf 10.2 dc characteristics: pic16c55x (commercial, industrial, extended) ? pic16lc55x(commercial, industrial, extended) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? ta ? +85c for industrial and 0c ? ta ? +70c for commercial and -40c ? ta ? +125c for automotive operating voltage v dd range as described in dc spec table 10-1 param. no. sym characteristic min typ? max unit conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1 pin is a schmitt trigger input. it is not recommended that the pic16c55x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on applied voltage level. the specified levels represent nor- mal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin.
pic16c55x ds40143e-page 80 preliminary ? 1996-2013 microchip technology inc. 10.3 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 10-5: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp ck clkout os osc1 io i/o port t0 t0cki mc mclr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 load condition 2
? 1996-2013 microchip technology inc. preliminary ds40143e-page 81 pic16c55x 10.4 timing diagrams and specifications figure 10-6: exter nal clock timing table 10-1: external clock timing requirements parameter no. sym characteristic min typ? max units conditions fos external clkin frequency (1) dc ? 4 mhz xt and rc osc mode, v dd =5.0v dc ? 20 mhz hs osc mode dc ? 200 khz lp osc mode oscillator frequency (1) dc ? 4 mhz rc osc mode, v dd =5.0v 0.1 ? 4 mhz xt osc mode 1 ? 20 mhz hs osc mode dc ? 200 khz lp osc mode 1 tosc external clkin period (1) 250 ? ? ns xt and rc osc mode 50 ? ? ns hs osc mode 5?? ? s lp osc mode oscillator period (1) 250 ? ? ns rc osc mode 250 ? 10,000 ns xt osc mode 50 ? 1,000 ns hs osc mode 5?? ? s lp osc mode 2 tcy instruction cycle time (1) 1.0 fos/4 dc ? st cy =f os /4 3* tosl, to sh external clock in (osc1) high or low time 100* ? ? ns xt osc mode 2* ? ? ? s lp osc mode 20* ? ? ns hs osc mode 4* tosr, to s f external clock in (osc1) rise or fall time 25* ? ? ns xt osc mode 50* ? ? ns lp osc mode 15* ? ? ns hs osc mode * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0 v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-bas e period. all specified values are based on characterization data for that particular oscillator ty pe under standard operating conditi ons with the device executing code. exceeding these specified limits may result in an uns table oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1 pin. ? when an external clock input is used, the ?max.? cycl e time limit is ?dc? (no clock) for all devices. osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
pic16c55x ds40143e-page 82 preliminary ? 1996-2013 microchip technology inc. figure 10-7: clko ut and i/o timing 22 23 note 1: all tests must be done with specified capacitance loads (figure 10-5) 50 pf on i/o pins and clkout. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
? 1996-2013 microchip technology inc. preliminary ds40143e-page 83 pic16c55x table 10-2: clkout and i/o timing requirements parameter # sym characteristic min typ? max units 10* tosh2ckl osc1 ? to clkout ?? (1) ? ? 75 ? 200 400 ns ns 11* tosh2ckh osc1 ? to clkout ? (1) ? ? 75 ? 200 400 ns ns 12* tckr clkout rise time (1) ? ? 35 ? 100 200 ns ns 13* tckf clkout fall time (1) ? ? 35 ? 100 200 ns ns 14* tckl2iov clkout ? to port out valid (1) ? ? 20 ns 15* tiov2ckh port in valid before clkout ? (1) tosc +200 ns tosc +400 ns ? ? ? ? ns ns 16* tckh2ioi port in hold after clkout ? (1) 0??ns 17* tosh2iov osc1 ? (q1 cycle) to port out valid ? ? 50 150 300 ns ns 18* tosh2ioi osc1 ? (q2 cycle) to port input invalid (i/o in hold time) 100 200 ? ? ? ? ns ns 19* tiov2osh port input valid to osc1 ?? (i/o in setup time) 0 ? ? ns 20* tior port output rise time ? ? 10 ? 40 80 ns ns 21* tiof port output fall time ? ? 10 ? 40 80 ns ns 22* tinp rb0/int pin high or low time 25 40 ? ? ? ? ns ns 23* trbp rb<7:4> change interrupt high or low time tcy ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: measurements are taken in rc mode where clkout output is 4 x t osc .
pic16c55x ds40143e-page 84 preliminary ? 1996-2013 microchip technology inc. figure 10-8: reset, watchdog timer, os cillator start-up timer and power-up timer timing table 10-3: reset, watchdog timer, oscillator start-up timer and power-up timer requirements param no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2000 ? ? ns -40 ? to +85 ? c 31 twdt watchdog timer timeout period (no prescaler) 7* 18 33* ms v dd = 5.0v, -40 ? to +85 ? c 32 tost oscillation start-up timer period ? 1024 t osc ??t osc = osc1 period 33 tpwrt power-up timer period 28* 72 132* ms v dd = 5.0v, -40 ? to +85 ? c 34 t ioz i/o hi-impedance from mclr low ? 2.0* ? s * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt timeout osc timeout internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34
? 1996-2013 microchip technology inc. preliminary ds40143e-page 85 pic16c55x figure 10-9: timer0 clock timing table 10-4: timer0 clock requirements figure 10-10: load conditions param no. sym characteristic min typ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 41 tt0l t0cki low pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 42 tt0p t0cki period t cy + 40 * n ? ? ns n = prescale value (1, 2, 4, ..., 256) * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. 41 42 40 ra4/t0cki tmr0 v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 load condition 2
pic16c55x ds40143e-page 86 preliminary ? 1996-2013 microchip technology inc. notes:
? 1996-2013 microchip technology inc. preliminary ds40143e-page 87 pic16c55x 11.0 packaging information 11.1 package marking information 28-lead ssop xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example 0025 cba pic16c557 -04i / ss123 18-lead pdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example 9823 cba pic16c558 -04i / p456 20-lead ssop yywwnnn xxxxxxxxxxx example -04/ss218 0020 cbp pic16c558 xxxxxxxxxxx 28-lead pdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example 9823 cba pic16c557 -04i / p456 legend: xx...x customer-specific information ? y year code (last digit of calendar year) ? yy year code (last 2 digits of calendar year) ? ww week code (week of january 1 is week ?01?) ? nnn alphanumeric traceability code ? pb-free jedec designator for matte tin (sn) ? * this package is pb-free. the pb-free jedec designator ( ) ? can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
pic16c55x ds40143e-page 88 preliminary ? 1996-2013 microchip technology inc. package marking information (cont?d) 18-lead soic (.300?) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example 9818 cdk pic16c558 -04i / s0218 xxxxxxxxxxxx 28-lead soic (.300?) xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example 9823 cba pic16c557 -04i / p456 xxxxxxxxxxxxxxxxxxxx 18-lead cerdip windowed example xxxxxxxx xxxxxxxx yywwnnn 16c558 /jw 9801 cba 28-lead cerdip windowed example xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn 16c557 /jw 9801 cba
? 1996-2013 microchip technology inc. preliminary ds40143e-page 89 pic16c55x 18-lead plastic dual in-line (p) ? 300 mil (pdip) 15 10 5 15 10 5 ? mold draft angle bottom 15 10 5 15 10 5 ? mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.46 1.14 .070 .058 .045 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 22.99 22.80 22.61 .905 .898 .890 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n e1 c eb ? e ? p a2 l b1 b a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-007 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c55x ds40143e-page 90 preliminary ? 1996-2013 microchip technology inc. 28-lead skinny plastic dual in-line (sp) ? 300 mil (pdip) 15 10 5 15 10 5 ? mold draft angle bottom 15 10 5 15 10 5 ? mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb ? e ? p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1996-2013 microchip technology inc. preliminary ds40143e-page 91 pic16c55x 18-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle ? 048048 15 12 0 15 12 0 ? mold draft angle bottom 15 12 0 15 12 0 ? mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.30 0.27 0.23 .012 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 11.73 11.53 11.33 .462 .454 .446 d overall length 7.59 7.49 7.39 .299 .295 .291 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units l ? c ? h 45 ? 1 2 d p n b e1 e ? a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-051 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c55x ds40143e-page 92 preliminary ? 1996-2013 microchip technology inc. 28-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle top ? 048048 15 12 0 15 12 0 ? mold draft angle bottom 15 12 0 15 12 0 ? mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c ? 45 ? h ? a2 ? a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1996-2013 microchip technology inc. preliminary ds40143e-page 93 pic16c55x 18-lead ceramic dual in-line with window (jw) ? 300 mil (cerdip) 3.30 3.56 3.81 5.33 5.08 4.83 .210 .200 .190 w2 window length .150 .140 .130 w1 window width 10.80 9.78 8.76 .425 .385 .345 eb overall row spacing 0.53 0.47 0.41 .021 .019 .016 b lower lead width 1.52 1.40 1.27 .060 .055 .050 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.81 3.49 3.18 .150 .138 .125 l tip to seating plane 23.37 22.86 22.35 .920 .900 .880 d overall length 7.49 7.37 7.24 .295 .290 .285 e1 ceramic pkg. width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.76 0.57 0.38 .030 .023 .015 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 4.95 4.64 4.32 .195 .183 .170 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n w2 e1 w1 c eb e p l a2 b b1 a a1 * controlling parameter significant characteristic jedec equivalent: mo-036 drawing no. c04-010 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c55x ds40143e-page 94 preliminary ? 1996-2013 microchip technology inc. 28-lead ceramic dual in-line with window (jw) ? 300 mil (cerdip) 3.30 3.56 3.81 7.87 7.62 7.37 .310 .300 .290 w2 window length .150 .140 .130 w1 window width 10.80 9.78 8.76 .425 .385 .345 eb overall row spacing 0.53 0.47 0.41 .021 .019 .016 b lower lead width 1.65 1.46 1.27 .065 .058 .050 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.68 3.56 3.43 .145 .140 .135 l tip to seating plane 37.72 37.02 36.32 1.485 1.458 1.430 d overall length 7.49 7.37 7.24 .295 .290 .285 e1 ceramic pkg. width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.76 0.57 0.38 .030 .023 .015 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 4.95 4.64 4.32 .195 .183 .170 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n w2 w1 e1 e eb p a2 l b1 b a1 a * controlling parameter c significant characteristic jedec equivalent: mo-058 drawing no. c04-080 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1996-2013 microchip technology inc. preliminary ds40143e-page 95 pic16c55x 20-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) 10 5 0 10 5 0 ? mold draft angle bottom 10 5 0 10 5 0 ? mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 ? foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 7.34 7.20 7.06 .289 .284 .278 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.18 7.85 7.59 .322 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c ? ? ? a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-150 drawing no. c04-072 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16c55x ds40143e-page 96 preliminary ? 1996-2013 microchip technology inc. 28-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-150 drawing no. c04-073 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 ? mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 ? foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 10.34 10.20 10.06 .407 .402 .396 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.10 7.85 7.59 .319 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters* inches units 2 1 d p n b e1 e l ? c ? ? a2 a1 a ? significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1996-2013 microchip technology inc. preliminary ds40143e-page 97 pic16c55x appendix a: enhancements the following are the list of enhancements over the pic16c5x microcontroller family: 1. instruction word length is increased to 14 bits. this allows larger page sizes both in program memory (4k now as opposed to 512 before) and register file (up to 128 bytes now versus 32 bytes before). 2. a pc high latch register (pclath) is added to handle program memory paging. pa2, pa1, pa0 bits are removed from status register. 3. data memory paging is slightly redefined. status register is modified. 4. four new instructions have been added: return , retfie , addlw , and sublw . ? two instructions tris and option are being phased out although they are kept for compatibility with pic16c5x. 5. option and tris registers are made addressable. 6. interrupt capability is added. interrupt vector is at 0004h. 7. stack size is increased to 8 deep. 8. reset vector is changed to 0000h. 9. reset of all registers is revised. three different reset (and wake-up) types are recognized. registers are reset differently. 10. wake-up from sleep through interrupt is added. 11. two separate timers, oscillator start-up timer (ost) and power-up timer (pwrt) are included for more reliable power-up. these timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. portb has weak pull-ups and interrupt-on- change feature. 13. timer0 clock input, t0cki pin is also a port pin (ra4/t0cki) and has a tris bit. 14. fsr is made a full 8-bit register. 15. ?in-circuit programming? is made possible. the user can program pic16c55x devices using only five pins: v dd , v ss , v pp , rb6 (clock) and rb7 (data in/out). 16. pcon status register is added with a power-on reset (por ) status bit. 17. code protection scheme is enhanced such that portions of the program memory can be protected, while the remainder is unprotected. 18. porta inputs are now schmitt trigger inputs. appendix b: compatibility to convert code written for pic16c5x to pic16c55x, the user should take the following steps: 1. remove any program memory page select operations (pa2, pa1, pa0 bits) for call , goto . 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any data memory page switching. redefine data variables to reallocate them. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to 0000h. appendix c: revision history revision e (january 2013) added a note to each package outline drawing.
pic16c55x ds40143e-page 98 preliminary ? 1996-2013 microchip technology inc. notes:
? 1996-2013 microchip technology inc. preliminary ds40143e-page 99 pic16c55x index a addlw instruction ............................................................. 55 addwf instruction ............................................................. 55 andlw instruction ............................................................. 55 andwf instruction ............................................................. 55 architectural overview .......................................................... 9 assembler mpasm assembler ..................................................... 67 b bcf instruction ................................................................... 56 block diagram timer0....................................................................... 47 tmr0/wdt prescaler .......................................... 50 bsf instruction ................................................................... 56 btfsc instruction............................................................... 56 btfss instruction ............................................................... 57 c call instruction ................................................................. 57 clocking scheme/instruction cycle .................................... 12 clrf instruction ................................................................. 57 clrw instruction ................................................................ 58 clrwdt instruction ........................................................... 58 code protection .................................................................. 46 comf instruction ................................................................ 58 configuration bits................................................................ 31 d data memory organization ................................................. 13 decf instruction................................................................. 58 decfsz instruction ............................................................ 59 development support ......................................................... 67 e errata .................................................................................... 3 external crystal oscillator circuit ....................................... 34 g general purpose register file ............................................ 13 goto instruction ................................................................ 59 i i/o ports .............................................................................. 23 i/o programming considerations........................................ 28 icepic in-circuit emulator ................................................. 68 id locations ........................................................................ 46 incf instruction .................................................................. 59 incfsz instruction ............................................................. 60 in-circuit serial programming ............................................. 46 indirect addressing, indf and fsr registers ................... 21 instruction flow/pipelining .................................................. 12 instruction set addlw ....................................................................... 55 addwf....................................................................... 55 andlw ....................................................................... 55 andwf....................................................................... 55 bcf............................................................................. 56 bsf ............................................................................. 56 btfsc ........................................................................ 56 btfss ........................................................................ 57 call ........................................................................... 57 clrf........................................................................... 57 clrw ......................................................................... 58 clrwdt .................................................................... 58 comf ......................................................................... 58 decf.......................................................................... 58 decfsz ..................................................................... 59 goto ......................................................................... 59 incf ........................................................................... 59 incfsz....................................................................... 60 iorlw ........................................................................ 60 iorwf........................................................................ 60 movf ......................................................................... 61 movlw ...................................................................... 60 movwf...................................................................... 61 nop............................................................................ 61 option...................................................................... 61 retfie....................................................................... 62 retlw ....................................................................... 62 return..................................................................... 62 rlf............................................................................. 62 rrf ............................................................................ 63 sleep ........................................................................ 63 sublw ....................................................................... 63 subwf....................................................................... 64 swapf ....................................................................... 64 tris ........................................................................... 64 xorlw....................................................................... 65 xorwf ...................................................................... 65 instruction set summary .................................................... 53 int interrupt ....................................................................... 42 intcon register................................................................ 19 interrupts ............................................................................ 41 iorlw instruction .............................................................. 60 iorwf instruction .............................................................. 60 k k ee l oq evaluation and programming tools...................... 70 m movf instruction................................................................ 61 movlw instruction............................................................. 60 movwf instruction ............................................................ 61 mplab c17 and mplab c18 c compilers ....................... 67 mplab icd in-circuit debugger ........................................ 69 mplab ice high performance universal in-circuit emulator with mplab ide ................................................................. 68 mplab integrated development environment software.... 67 mplink object linker/mplib object librarian .................. 68 n nop instruction .................................................................. 61 o one-time-programmable (otp) devices ............................ 7 option instruction ............................................................ 61 option register................................................................ 18 oscillator configurations..................................................... 33 oscillator start-up timer (ost) .......................................... 36 p pcl and pclath............................................................... 21 pcon register ................................................................... 20 picdem 1 low cost pic mcu demonstration board........ 69 picdem 17 demonstration board...................................... 70 picdem 2 low cost pic16cxx demonstration board ..... 69 picdem 3 low cost pic16cxxx demonstration board ... 70
pic16c55x ds40143e-page 100 preliminary ? 1996-2013 microchip technology inc. picstart plus entry level development programmer .... 69 port rb interrupt ................................................................. 42 porta................................................................................ 23 portb.......................................................................... 25, 27 power control/status register (pcon) .............................. 37 power-down mode (sleep)............................................... 45 power-on reset (por) ...................................................... 36 power-up timer (pwrt)..................................................... 36 prescaler ............................................................................. 49 pro mate ii universal device programmer ..................... 69 program memory organization ........................................... 13 q quick-turnaround-production (qtp) devices ...................... 7 r rc oscillator ....................................................................... 34 reset................................................................................... 35 retfie instruction.............................................................. 62 retlw instruction .............................................................. 62 return instruction............................................................ 62 rlf instruction.................................................................... 62 rrf instruction ................................................................... 63 s serialized quick-turnaround-production (sqtp) devices ... 7 sleep instruction ............................................................... 63 software simulator (mplab sim)....................................... 68 special features of the cpu............................................... 31 special function registers ................................................. 15 stack ................................................................................... 21 status register.................................................................... 17 sublw instruction.............................................................. 63 subwf instruction.............................................................. 64 swapf instruction.............................................................. 64 t timer0 timer0 ....................................................................... 47 timer0 (tmr0) interrupt ........................................... 47 timer0 (tmr0) module ............................................. 47 tmr0 with external clock........................................... 49 timer1 switching prescaler assignment................................. 51 timing diagrams and specifications................................... 81 tmr0 interrupt .................................................................... 42 tris instruction .................................................................. 64 trisa.................................................................................. 23 trisb............................................................................ 25, 27 w watchdog timer (wdt) ...................................................... 43 www, on-line support........................................................ 3 x xorlw instruction ............................................................. 65 xorwf instruction ............................................................. 65
? 1996-2013 microchip technology inc. ds40143e-page 101 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
ds40143e-page 102 ? 1996-2013 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds40143e 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 1996-2013 microchip technology inc. preliminary ds40143e-page 103 pic16c55x product identification system to order or obtain information, e.g. , on pricing or delivery, refer to the factory or the listed sales office. * jw devices are uv erasable and can be programmed to any device c onfiguration. jw devices meet the electrical requirement of each oscillator type. sales and support part no. x /xx xxx pattern package temperature range device device pic17c756: standard v dd range pic17c756t: (tape and reel) pic17lc756: extended v dd range temperature range - = 0 ? c to +70 ? c i= -40 ? c to +85 ? c package cl = windowed lcc pt = tqfp l=plcc pattern qtp, sqtp, rom code (factory specified) or ? special requirements. blank for otp and ? windowed devices. examples: a) pic17c756?16l commercial temp., ? plcc package, 16 mhz, ? normal v dd limits b) pic17lc756?08/pt commercial temp., ? tqfp package, 8mhz, ? extended v dd limits c) pic17c756?33i/pt industrial temp., ? tqfp package, 33 mhz, ? normal v dd limits data sheets products supported by a preliminary data sheet may have an e rrata sheet describing minor operational differences and recom- mended workarounds. to determine if an erra ta sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip worldwide site (www.microchip.com)
pic16c55x ds40143e-page 104 preliminary ? 1996-2013 microchip technology inc. notes:
? 1996-2013 microchip technology inc. preliminary ds40143e-page 105 pic16c55x notes:
pic16c55x ds40143e-page 106 preliminary ? 1996-2013 microchip technology inc.
? 1996-2013 microchip technology inc. preliminary ds40143e-page 107 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 1996-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620769737 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
ds40143e-page 108 preliminary ? 1996-2013 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 11/29/12

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